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IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)
Volumn , Issue , 2003, Pages 169-172
Novel process techniques for fabricating high density trench MOSFETs with self-aligned N+/P+ source formed on the trench side wall
Author keywords

[No Author keywords available]
Indexed keywords

COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC CONTACTS; ELECTRIC RESISTANCE;
EID: 0042440615     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)
References (4)
  • 1
    • 0034449612 scopus 로고    scopus 로고
    • A 0.35 μm trench gate MOSFET with an ultra low on state resistance and a high destruction immunity during the inductive switching
    • thISPSD (2000), p. 377.
    • (2000) thISPSD , pp. 377
    • Narazaki, A.1
  • 2
    • 0036049980 scopus 로고    scopus 로고
    • Fully self-aligned power trench-MOSFET utilitsing 1 μm pitch and 0.2 μm trench width
    • th ISPSD (2002) p. 29.
    • (2002) th ISPSD , pp. 29
    • Peake, S.T.1
  • 3
    • 0034829322 scopus 로고    scopus 로고
    • An ultra dense trench-gated power MOSFET technology using a self-aligned process
    • th ISPSD (2001) p. 147.
    • (2001) th ISPSD , pp. 147
    • Zeng, J.1
  • 4
    • 0034447195 scopus 로고    scopus 로고
    • Trench corner rounding technology using hydrogen annealing for highly reliable trench DMOSFETs
    • th ISPSD (2000), p. 87.
    • (2000) th ISPSD , pp. 87
    • Kim, S.-G.1

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.