Test scheduling for network-on-chip with BIST and precedence constraints

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 1369-1378

  Liu, Chunsheng ^a   Cota, Érika ^b   Sharif, Hamid ^a   Pradhan, D K ^c  

^a UNIVERSITY OF NEBRASKA LINCOLN   (United States)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^c UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; BROADCASTING; BUILT-IN SELF TEST; CONSTRAINT THEORY; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; ROUTERS; SCHEDULING;

NETWORK-ON-A-CHIP (NOC); PRECEDENCE CONSTRAINTS; TEST ACCESS MECHANISM (TAM); TEST SCHEDULING;

INTEGRATED CIRCUIT TESTING;

EID: 18144395845     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)

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