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Volumn , Issue , 2003, Pages 612-621

Power-aware NoC Reuse on the Testing of Core-based Systems

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; COMMUNICATION SYSTEMS;

EID: 0142215984     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (67)

References (19)
  • 1
    • 84893687806 scopus 로고    scopus 로고
    • A Generic Architecture for On-Chip Packet-Switched Interconnections
    • Mar.
    • P. Guerrier and A. Greiner. A Generic Architecture for On-Chip Packet-Switched Interconnections. In Design, Automation and Test in Europe, pages 250-256, Mar. 2000.
    • (2000) Design, Automation and Test in Europe , pp. 250-256
    • Guerrier, P.1    Greiner, A.2
  • 2
    • 0036149420 scopus 로고    scopus 로고
    • Networks on Chips: A New SOC Paradigm
    • January
    • L. Benini and G. D. Micheli. Networks on Chips: a New SOC Paradigm. IEEE Computer, pages 70-78, January 2002.
    • (2002) IEEE Computer , pp. 70-78
    • Benini, L.1    Micheli, G.D.2
  • 3
    • 0034848112 scopus 로고    scopus 로고
    • Route Packets, Not Wires: On-Chip Interconnection Networks
    • Jun.
    • W. J. Daly and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. In Design Automation Conference, Jun. 2001.
    • (2001) Design Automation Conference
    • Daly, W.J.1    Towles, B.2
  • 10
    • 0032308284 scopus 로고    scopus 로고
    • A Structured Test Re-use Methodology for Core-based System Chips
    • Oct.
    • P. Varma and S. Bhatia. A Structured Test Re-use Methodology for Core-based System Chips. In International Test Conference, pages 294-302, Oct. 1998.
    • (1998) International Test Conference , pp. 294-302
    • Varma, P.1    Bhatia, S.2
  • 11
    • 0036143962 scopus 로고    scopus 로고
    • A Complete Strategy for Testing an On-Chip Multiprocessor Architecture
    • Jan-Feb
    • C. Aktouf. A Complete Strategy for Testing an On-Chip Multiprocessor Architecture. IEEE Design & Test of Computers, 19(l):18-28, Jan-Feb 2002.
    • (2002) IEEE Design & Test of Computers , vol.19 , Issue.1 , pp. 18-28
    • Aktouf, C.1
  • 12
    • 0011840160 scopus 로고    scopus 로고
    • A Packet Switching Communication-Based Test Access Mechanism for System Chips
    • Mar.
    • M. Nahvi and A. Ivanov. A Packet Switching Communication-Based Test Access Mechanism for System Chips. In IEEE European Test Workshop, Mar. 2001.
    • (2001) IEEE European Test Workshop
    • Nahvi, M.1    Ivanov, A.2
  • 13
    • 0031163752 scopus 로고    scopus 로고
    • Scheduling Tests for VLSI Systems under Power Constraints
    • June
    • R. M. Chou, K. K. Saluja, and V. D. Agrawal. Scheduling Tests for VLSI Systems Under Power Constraints. IEEE Transacions on VLSI Systems, 5(2):175-185, June 1997.
    • (1997) IEEE Transacions on VLSI Systems , vol.5 , Issue.2 , pp. 175-185
    • Chou, R.M.1    Saluja, K.K.2    Agrawal, V.D.3
  • 15
    • 0034995151 scopus 로고    scopus 로고
    • Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
    • May
    • V. Iyengar and K. Chakrabarty. Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. In IEEE VLSI Test Symposium, pages 368-374, May 2001.
    • (2001) IEEE VLSI Test Symposium , pp. 368-374
    • Iyengar, V.1    Chakrabarty, K.2
  • 17
    • 0003937287 scopus 로고    scopus 로고
    • Interconnection Networks: An Engineering Approach
    • Los Alamitos, CA
    • J. Duato and et. al. Interconnection Networks: an Engineering Approach. IEEE Computer Society Press, Los Alamitos, CA, 1997.
    • (1997) IEEE Computer Society Press
    • Duato, J.1
  • 19


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.