Robust ultra-low power sub-threshold DTMOS logic

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2000, Pages 25-30

  Soeleman, Hendrawan ^a   Roy, Kaushik ^a   Paul, Bipul ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC CIRCUITS; MOS DEVICES; TRANSISTORS;

DIGITAL SUB-THRESHOLD LOGIC CIRCUITS; SUB-THRESHOLD DYNAMIC THRESHOLD TRANSISTORS;

POWER ELECTRONICS;

EID: 0033661304     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/344166.344187     Document Type: Article

References (0)