-
1
-
-
22644449714
-
High-Level Design Verification of Microprocessors via Error Modeling
-
October
-
D. Van Campenhout, H. Al-Asaad, J.P. Hayes, T. Mudge, R.B. Brown, "High-Level Design Verification of Microprocessors via Error Modeling," ACM Transactions on Design Automation of Electronic Systems, Vol. 3, No. 4 (October 1998), pp. 581-599.
-
(1998)
ACM Transactions on Design Automation of Electronic Systems
, vol.3
, Issue.4
, pp. 581-599
-
-
Van Campenhout, D.1
Al-Asaad, H.2
Hayes, J.P.3
Mudge, T.4
Brown, R.B.5
-
3
-
-
0343371798
-
Collection and Analysis of Microprocessor Design Errors
-
October-December
-
D. Van Campenhout, T. Mudge, J.P. Hayes, "Collection and Analysis of Microprocessor Design Errors," IEEE Design & Test of Computers, Vol. 17, No. 4 (October-December 2000), pp. 51-60.
-
(2000)
IEEE Design & Test of Computers
, vol.17
, Issue.4
, pp. 51-60
-
-
Van Campenhout, D.1
Mudge, T.2
Hayes, J.P.3
-
5
-
-
8744290910
-
Integrating Formal Verification into an Advanced Computer Architecture Course
-
June
-
M.N. Velev, "Integrating Formal Verification into an Advanced Computer Architecture Course," ASEE Annual Conference & Exposition, June 2003.
-
(2003)
ASEE Annual Conference & Exposition
-
-
Velev, M.N.1
-
7
-
-
0142237074
-
-
Intel Corporation, Intel Pentium® Processor, http://developer.intel.com/ design/pentium.
-
Intel Pentium® Processor
-
-
-
10
-
-
0142174970
-
-
Ibm, Inc., Powerpc 440, http://www-3.ibm.com/chips/techlib/techlib.nsf/products/ powerpc_440_embedded_core.
-
Powerpc
, vol.440
-
-
-
12
-
-
84958753231
-
EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality and Conservative Transformations
-
G. Berry, H. Comon, and A. Finkel, eds., LNCS 2102, Springer-Verlag, July
-
Velev, and R.E. Bryant, "EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality and Conservative Transformations," Computer-Aided Verification (CAV '01), G. Berry, H. Comon, and A. Finkel, eds., LNCS 2102, Springer-Verlag, July 2001, pp. 235-240.
-
(2001)
Computer-aided Verification (CAV '01)
, pp. 235-240
-
-
Velev, M.N.1
Bryant, R.E.2
-
13
-
-
84952793183
-
Experience with Term Level Modeling and Verification of the M·CORE™ Microprocessor Core
-
November
-
S. Lahiri, C. Pixley, and K. Albin, "Experience with Term Level Modeling and Verification of the M·CORE™ Microprocessor Core, " 6th Annual IEEE International Workshop on High Level Design, Validation and Test (HLDVT '01), November 2001, pp. 109-114.
-
(2001)
6th Annual IEEE International Workshop on High Level Design, Validation and Test (HLDVT '01)
, pp. 109-114
-
-
Lahiri, S.1
Pixley, C.2
Albin, K.3
-
14
-
-
84958772916
-
Automated Verification of Pipelined Microprocessor Control
-
D.L. Dill, ed., LNCS 818, Springer-Verlag, June
-
J.R. Burch, and D.L. Dill, "Automated Verification of Pipelined Microprocessor Control," Computer-Aided Verification (CAV '94), D.L. Dill, ed., LNCS 818, Springer-Verlag, June 1994, pp. 68-80.
-
(1994)
Computer-aided Verification (CAV '94)
, pp. 68-80
-
-
Burch, J.R.1
Dill, D.L.2
-
15
-
-
0032690808
-
Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors
-
June
-
M.N. Velev, and R.E. Bryant, "Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors," 36th Design Automation Conference (DAC '99), June 1999.
-
(1999)
36th Design Automation Conference (DAC '99)
-
-
Velev, M.N.1
Bryant, R.E.2
-
18
-
-
84861449103
-
Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Prepositional Logic
-
L. Pierre, and T. Kropf, eds., LNCS 1703, Springer-Verlag, September
-
M.N. Velev, and R.E. Bryant, "Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Prepositional Logic," Correct Hardware Design and Verification Methods (CHARME '99), L. Pierre, and T. Kropf, eds., LNCS 1703, Springer-Verlag, September 1999, pp. 37-53.
-
(1999)
Correct Hardware Design and Verification Methods (CHARME '99)
, pp. 37-53
-
-
Velev, M.N.1
Bryant, R.E.2
-
19
-
-
84958791713
-
Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Prepositional Logic
-
January
-
R.E. Bryant, S. German, and M.N. Velev, "Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Prepositional Logic," ACM Transactions on Computational Logic (TOCL), Vol. 2, No. 1 (January 2001), pp. 93-134.
-
(2001)
ACM Transactions on Computational Logic (TOCL)
, vol.2
, Issue.1
, pp. 93-134
-
-
Bryant, R.E.1
German, S.2
Velev, M.N.3
-
20
-
-
0034852165
-
Chaff: Engineering an Efficient SAT Solver
-
June
-
M.W. Moskewicz, C.F. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an Efficient SAT Solver," 38th Design Automation Conference (DAC '01), June 2001, pp. 530-535.
-
(2001)
38th Design Automation Conference (DAC '01)
, pp. 530-535
-
-
Moskewicz, M.W.1
Madigan, C.F.2
Zhao, Y.3
Zhang, L.4
Malik, S.5
-
21
-
-
0035209012
-
Efficient Conflict Driven Learning in a Boolean Satisfiability Solver
-
November
-
L. Zhang, C.F. Madigan, M.W. Moskewicz, and S. Malik, "Efficient Conflict Driven Learning in a Boolean Satisfiability Solver," International Conference on Computer-Aided Design (ICCAD '01), November 2001.
-
(2001)
International Conference on Computer-aided Design (ICCAD '01)
-
-
Zhang, L.1
Madigan, C.F.2
Moskewicz, M.W.3
Malik, S.4
-
22
-
-
84893808653
-
BerkMin: A Fast and Robust Sat-Solver
-
March
-
E. Goldberg, and Y. Novikov, "BerkMin: A Fast and Robust Sat-Solver," Design, Automation, and Test in Europe (DATE '02), March 2002.
-
(2002)
Design, Automation, and Test in Europe (DATE '02)
-
-
Goldberg, E.1
Novikov, Y.2
-
23
-
-
84948174903
-
Relating Multi-Step and Single-Step Microprocessor Correctness Statements
-
M.D. Aagaard, and J.W. O'Leary, eds., LNCS 2517, Springer-Verlag, November
-
M.D. Aagaard, N.A. Day, and M. Lou, "Relating Multi-Step and Single-Step Microprocessor Correctness Statements," Formal Methods in Computer-Aided Design (FMCAD '02), M.D. Aagaard, and J.W. O'Leary, eds., LNCS 2517, Springer-Verlag, November 2002, pp. 123-141.
-
(2002)
Formal Methods in Computer-aided Design (FMCAD '02)
, pp. 123-141
-
-
Aagaard, M.D.1
Day, N.A.2
Lou, M.3
-
24
-
-
0142174971
-
A Framework for Superscalar Microprocessor Correctness Statements
-
M.D. Aagaard, B. Cook, N.A. Day, and R.B. Jones, "A Framework for Superscalar Microprocessor Correctness Statements," to appear in Software Tools for Technology Transfer (STTT), 2002.
-
(2002)
Software Tools for Technology Transfer (STTT)
-
-
Aagaard, M.D.1
Cook, B.2
Day, N.A.3
Jones, R.B.4
-
25
-
-
84903158789
-
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
-
LNCS 2031, Springer-Verlag
-
M.N. Velev, "Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors," Tools and Algorithms for the Construction and Analysis of Systems, LNCS 2031, Springer-Verlag, 2001.
-
(2001)
Tools and Algorithms for the Construction and Analysis of Systems
-
-
Velev, M.N.1
-
26
-
-
84863922391
-
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
-
LNCS 1427, Springer-Verlag, June
-
A. Goel, K. Sajid, H. Zhou, A. Aziz, and V. Singhal, "BDD Based Procedures for a Theory of Equality "with Uninterpreted Functions," ComputerAided Verification (CAV '98), LNCS 1427, Springer-Verlag, June 1998.
-
(1998)
ComputerAided Verification (CAV '98)
-
-
Goel, A.1
Sajid, K.2
Zhou, H.3
Aziz, A.4
Singhal, V.5
-
27
-
-
84957075583
-
Deciding Equality Formulas by Small-Domain Instantiations
-
LNCS 1633, Springer-Verlag, June
-
A. Pnueli, Y. Rodeh, O. Shtrichman, and M. Siegel, "Deciding Equality Formulas by Small-Domain Instantiations," Computer-Aided Verification (CAV '99), LNCS 1633, Springer-Verlag, June 1999, pp. 455-469.
-
(1999)
Computer-aided Verification (CAV '99)
, pp. 455-469
-
-
Pnueli, A.1
Rodeh, Y.2
Shtrichman, O.3
Siegel, M.4
-
28
-
-
0037331793
-
Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors
-
February
-
M.N. Velev, and R.E. Bryant, "Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors," Journal of Symbolic Computation (JSC), Vol. 35, No. 2 (February 2003), pp. 73-106.
-
(2003)
Journal of Symbolic Computation (JSC)
, vol.35
, Issue.2
, pp. 73-106
-
-
Velev, M.N.1
Bryant, R.E.2
-
30
-
-
0033684177
-
Formal Verification of Superscalar Microprocessors with Multicycle Functional Units, Exceptions, and Branch Prediction
-
June
-
M.N. Velev, and R.E. Bryant, "Formal Verification of Superscalar Microprocessors with Multicycle Functional Units, Exceptions, and Branch Prediction," 37th Design Automation Conference (DAC '00), June 2000.
-
(2000)
37th Design Automation Conference (DAC '00)
-
-
Velev, M.N.1
Bryant, R.E.2
-
31
-
-
0004318589
-
-
Intel Corporation, April
-
Intel Corporation, Pentium II Processor Specification Update, April 1999, http://www.intel.com/design/pentiumii/specupdt/.
-
(1999)
Pentium II Processor Specification Update
-
-
-
32
-
-
0142206120
-
Validating the Intel® Pentium® 4 Processor
-
1st Quarter
-
B. Bentley, and R. Gray, "Validating the Intel® Pentium® 4 Processor," Intel Technology Journal, 1st Quarter, 2001.
-
(2001)
Intel Technology Journal
-
-
Bentley, B.1
Gray, R.2
-
35
-
-
0032641334
-
Exploiting Symmetry When Verifying Transistor-Level Circuits by Symbolic Trajectory Evaluation
-
July
-
M. Pandey, and R.E. Bryant, "Exploiting Symmetry When Verifying Transistor-Level Circuits by Symbolic Trajectory Evaluation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 7 (July 1999), pp. 918-935.
-
(1999)
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems
, vol.18
, Issue.7
, pp. 918-935
-
-
Pandey, M.1
Bryant, R.E.2
-
38
-
-
0003601977
-
-
Ph.D. Thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, August
-
A. Jain, "Formal Hardware Verification by Symbolic Trajectory Evaluation," Ph.D. Thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, August 1997.
-
(1997)
Formal Hardware Verification by Symbolic Trajectory Evaluation
-
-
Jain, A.1
-
40
-
-
0001510331
-
Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories
-
March
-
C.-J.H. Seger, and R.E. Bryant, "Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories," Formal Methods in System Design, Vol. 6, No. 2 (March 1995), pp. 147-190.
-
(1995)
Formal Methods in System Design
, vol.6
, Issue.2
, pp. 147-190
-
-
Seger, C.-J.H.1
Bryant, R.E.2
-
41
-
-
0028195825
-
A Proof of the Non-Restoring Division Algorithm and Its Implementation on an ALU
-
L. Claesen, D. Verkest, and H. De Man, "A Proof of the Non-Restoring Division Algorithm and Its Implementation on an ALU," Formal Methods in System Design, Vol. 5 (1994), pp. 5-31.
-
(1994)
Formal Methods in System Design
, vol.5
, pp. 5-31
-
-
Claesen, L.1
Verkest, D.2
De Man, H.3
-
43
-
-
84958976579
-
Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization
-
LNCS 901, Springer-Verlag
-
J.W. O'Leary, M.E. Leeser, J. Hickey, and M.D. Aagaard, "Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization," Theorem Provers in Circuit Design: Theory, Practice and Experience (TPCD '94), LNCS 901, Springer-Verlag, 1995, pp. 52-71.
-
(1995)
Theorem Provers in Circuit Design: Theory, Practice and Experience (TPCD '94)
, pp. 52-71
-
-
O'Leary, J.W.1
Leeser, M.E.2
Hickey, J.3
Aagaard, M.D.4
-
44
-
-
0001582662
-
A Mechanically Checked Proof of IEEE Compliance of the Floating Point Multiplication, Division and Square Root Algorithms of the AMD K7 Processor
-
D.M. Russinoff, "A Mechanically Checked Proof of IEEE Compliance of the Floating Point Multiplication, Division and Square Root Algorithms of the AMD K7 Processor," LMS Journal of Computation and Mathematics, No. 1 (1998), pp. 148-200.
-
(1998)
LMS Journal of Computation and Mathematics
, Issue.1
, pp. 148-200
-
-
Russinoff, D.M.1
-
45
-
-
0035394259
-
Practical Formal Verification in Microprocessor Design
-
July-August
-
R.B. Jones, J.W. O'Leary, C.-J.H. Seger, M.D. Aagaard, and T.F. Melham, "Practical Formal Verification in Microprocessor Design," IEEE Design & Test of Computers, Vol. 18, No. 4 (July-August 2001).
-
(2001)
IEEE Design & Test of Computers
, vol.18
, Issue.4
-
-
Jones, R.B.1
O'Leary, J.W.2
Seger, C.-J.H.3
Aagaard, M.D.4
Melham, T.F.5
-
46
-
-
84957677881
-
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking
-
M. Srivas, and A. Camilleri, eds., LNCS 1166, Springer-Verlag, November
-
Y.-A. Chen, E. Clark, P.-H. Ho, Y. Hoskote, T. Kam, M. Khaira, J. O'Leary, and X. Zhao, "Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking," Formal Methods in Computer-Aided Design (FMCAD '96), M. Srivas, and A. Camilleri, eds., LNCS 1166, Springer-Verlag, November 1996, pp. 19-33.
-
(1996)
Formal Methods in Computer-aided Design (FMCAD '96)
, pp. 19-33
-
-
Chen, Y.-A.1
Clark, E.2
Ho, P.-H.3
Hoskote, Y.4
Kam, T.5
Khaira, M.6
O'Leary, J.7
Zhao, X.8
-
47
-
-
0035670976
-
An Efficient Graph Representation for Arithmetic Circuit Verification
-
December
-
Y.-A. Chen, and R.E. Bryant, "An Efficient Graph Representation for Arithmetic Circuit Verification," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 12 (December 2001), pp. 1442-1454.
-
(2001)
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems
, vol.20
, Issue.12
, pp. 1442-1454
-
-
Chen, Y.-A.1
Bryant, R.E.2
-
48
-
-
84896694043
-
Verification of Arithmetic Circuits Using Binary Moment Diagrams
-
May
-
R.E. Bryant, and Y.-A. Chen, "Verification of Arithmetic Circuits Using Binary Moment Diagrams," Software Tools for Technology Transfer (STTT), Vol. 3, No. 2 (May 2001), pp. 137-155.
-
(2001)
Software Tools for Technology Transfer (STTT)
, vol.3
, Issue.2
, pp. 137-155
-
-
Bryant, R.E.1
Chen, Y.-A.2
-
49
-
-
0036444835
-
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems
-
October
-
G Parthasarathy, M. K. Iyer, T. Feng, L.-C. Wang, K.-T. Cheng, M. S. Abadir. Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems," International Test Conference (ITC '02), October 2002.
-
(2002)
International Test Conference (ITC '02)
-
-
Parthasarathy, G.1
Iyer, M.K.2
Feng, T.3
Wang, L.-C.4
Cheng, K.-T.5
Abadir, M.S.6
-
50
-
-
0036058077
-
A Hybrid Verification Approach: Getting Deep into the Design
-
June
-
S. Hazelhurst, O. Weissberg, G Kamhi, and L. Fix, "A Hybrid Verification Approach: Getting Deep into the Design," 39th Design Automation Conference (DAC '02), June 2002, pp. 111-116.
-
(2002)
39th Design Automation Conference (DAC '02)
, pp. 111-116
-
-
Hazelhurst, S.1
Weissberg, O.2
Kamhi, G.3
Fix, L.4
|