Superscalar processor verification using efficient reductions of the logic of equality with uninterpreted functions to propositional logic

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1703, Issue , 1999, Pages 37-53

  Velev, Miroslav N ^a   Bryant, Randal E ^a,b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b Carnegie Mellon University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; FORMAL LOGIC; HARDWARE; RECONFIGURABLE HARDWARE;

AUTOMATIC TOOLS; LOGIC OF EQUALITIES; POSITIVE EQUALITY; PROPOSITIONAL LOGIC; SUPERSCALAR PROCESSOR; UNINTERPRETED FUNCTIONS; VERIFICATION METHOD;

PIPELINE PROCESSING SYSTEMS;

EID: 84861449103     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48153-2_5     Document Type: Conference Paper

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