EVC: A validity checker for the logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2102, Issue , 2001, Pages 235-240

  Velev, Miroslav N ^a   Bryant, Randal E ^a,b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b Carnegie Mellon University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; FORMAL VERIFICATION; RECONFIGURABLE HARDWARE; VERY LONG INSTRUCTION WORD ARCHITECTURE;

BOOLEAN SATISFIABILITY; LOGIC OF EQUALITIES; LOGIC OF EQUALITY WITH UNINTERPRETED FUNCTIONS AND MEMORY (EUFM); POSITIVE EQUALITY; SUPERSCALAR; UNINTERPRETED FUNCTIONS;

COMPUTER CIRCUITS;

EID: 84958753231     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44585-4_20     Document Type: Conference Paper

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