Verification of all circuits in a floating-point unit using word-level model checking

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1166, Issue , 1996, Pages 19-33

  Chen, Yirng An ^a   Clarke, Edmund ^a   Ho, Pei Hsin ^b   Hoskote, Yatin ^b   Kam, Timothy ^b   Khaira, Manpreet ^b   O’Leary, John ^b   Zhao, Xudong ^b  

^a Carnegie Mellon University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL ARITHMETIC; FORMAL METHODS; FORMAL VERIFICATION; INTEGRATING CIRCUITS; LOGIC CIRCUITS; PROGRAM PROCESSORS; RECONFIGURABLE HARDWARE;

ARITHMETIC CIRCUIT; FLOATING POINT UNITS; LARGE-SCALE APPLICATIONS; MODEL EXTRACTION; ROUNDING OPERATION; STATE OF THE ART; VERIFICATION METHODOLOGY; VERIFICATION TECHNIQUES;

MODEL CHECKING;

EID: 84957677881     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/BFb0031797     Document Type: Conference Paper

References (20)

1. D. E. Atkins. Higher-radix division using estimates of the divisor and partial remainders. IEEE Transactions on Computers, C-17(10):925-934, October 1968.
2. R.E.I. Beer, S. Ben-David, C. Eisner, and Avner Landver. Rulebase: an industry-oriented formal verification tool. In Proceedings of the 33rd Design Automation Conference. IEEE Computer Society Press, June 1996.
3. R. E. Bryant and Y. A. Chen. Verification of arithmetic functions with binary moment diagrams. In Proceedings of the 32nd A CM/IEEE Design Automation Conference, pages 535-541. IEEE Computer Society Press, June 1995.
4. R. E. Bryant. On the complexity of vlsi implementations and graph representations of boolean functions with application to integer multiplication. IEEE Transactions on Computers, 40(2):205-213, 1991.
5. R.E. Bryant. Bit-level analysis of an srt divider circuit. Technical report, Carnegie Mellon University, 1995.
6. M. Birman, A. Samuels, G. Chu, T. Chuk, L. Hu, J. McLeod, and J. Barnes. Developing the wt13170/3171 sparc floating-point coprocessors. IEEE Micro, pages 55-64, February 1990.
7. J. Bannur and A. Varma. The vlsi implementation of a square root algorithm. In Proceedings of the 7th Symposium on Computer Arithmetic, pages 159-165. IEEE Computer Society Press, 1985.
8. E. M. Clarke, M. Fujita, and X. Zhao. Hybrid decision diagrams – overcoming the limitations of mtbdds and brads. In Proceedings of the 1995 Proceedings of the IEEE International Conference on Computer Aided Design, pages 159-163. IEEE Computer Society Press, November 1995.
9. E. M. Clarke, M. Khaira, and X. Zhao. Word level symbolic model checking - a new approach for verifying arithmetic circuits. In Proceedings of the 33rd A CM/IEEE Design Automation Conference. IEEE Computer Society Press, June 1996.
10. E. M. Clarke, K. McMillan, X. Zhao, M. Fujita, and J. Yang. Spectral transforms for large boolean functions with applications to technology mapping. In Proceedings of the 30th ACM/IEEE Design Automation Conference, pages 54-60. IEEE Computer Society Press, June 1993.
11. T. Coe. Inside the pentium fdiv bug. Dr. Dobbs Journal, 20(4):129-135, April 1995.
12. C. V. Frieman. Statistical analysis of certain arithmetic binary division algorithms. IRE Transaction, pages 91-103, January 1961.
13. K. Hamaguchi, A. Morita, and S. Yajima. Efficient construction of binary moment diagrams for verifying arithmetic circuits. In Proceedings of the 1995 IEEE International Conference on Computer Aided Design, pages 78-82, November 1995.
14. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kanfmann, 1996.
15. R. P. Kurshan and L. Lamport. Verification of a multiplier: 64 bits and beyond. In C. Courcoubetis, editor, Proceedings of the Fifth Workshop on Computer-Aided Verification, June/July 1993.
16. K. L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, 1993.
17. J. O'Leary, M. Leeser, J. Hickey, and M. Aagaard. Non-restoring integer square root: a case study in design by principled optimization. In Proceedings of the Theorem Provers in Circuit Design '94, volume 901 of Lecture Notes in Computer Science. Springer-Verlag, 1995.
18. R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Intl. Conf. on Computer Aided Design, Santa Clara, Ca., November 1993.
19. H. P. Sharangpani and M. L. Barton. Statistical analysis of floating point flaw in the pentium processor(1994). Technical report, Intel Corporation, November 1994.
20. D. Verkest, L. Claesen, and H. De Man. A proof of the nonrestoring division algorithm and its implementation on an aln. Formal Methods in System Design, 4:5-31, January 1994.