Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors

Proceedings - Design Automation Conference

Volumn , Issue , 1999, Pages 397-401

  Velev, Miroslav N ^a   Bryant, Randal E ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; FORMAL LOGIC; PIPELINE PROCESSING SYSTEMS;

FORMAL VERIFICATION; INSTRUCTION SET ARCHITECTURE (ISA);

MICROPROCESSOR CHIPS;

EID: 0032690808     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/309847.309967     Document Type: Conference Paper

References (15)