Combining ATPG and symbolic simulation for efficient validation of embedded array systems

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 203-212

  Parthasarathy, Ganapathy ^a   Iyer, Madhu K ^a   Feng, Tao ^a   Wang, Li C ^a   Cheng, Kwang Ting Tim ^a   Abadir, Magdy S ^b  

^a University of California   (United States)

^b Motorala   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DECISION THEORY; MICROPROCESSOR CHIPS; SHIFT REGISTERS;

EMBEDDED ARRAY SYSTEMS; MEMORY MANAGEMENT UNIT; ORDERED BOOLEAN DECISION DIAGRAMS; SYMBOLIC SIMULATION; SYMBOLIC TRAJECTORY EVALUATION;

EMBEDDED SYSTEMS;

EID: 0036444835     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

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