High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni SALICIDE

Technical Digest-International Electron Devices Meeting

Volumn , Issue , 2001, Pages 641-644

  Inaba, S ^a   Okano, K ^a   Matsuda, S ^a   Fujiwara, M ^a   Hokazono, A ^a   Adachi, K ^a   Ohuchi, K ^a   Suto, H ^a   Fukui, H ^a   Shimizu, T ^b   Mori, S ^b   Oguma, H ^b   Murakoshi, A ^b   Itani, T ^b   Iinuma, T ^b   Kudo, T ^b   Shibata, H ^b   Taniguchi, S ^b   Matsushita, T ^b   Magoshi, S ^b   Watanabe, Y ^b   Takayanagi, M ^a   Azuma, A ^a   Oyamatsu, H ^a   Suguro, K ^b   Katsumata, Y ^a   Toyoshima, Y ^a   Ishiuchi, H ^a   more..

^a TOSHIBA CORPORATION   (Japan)

^b Process and Manufacturing Engineering Center   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC DEVICES; ELECTRIC CURRENTS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; NITROGEN COMPOUNDS; OPTIMIZATION; PERFORMANCE; POLYSILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; TRANSMISSION ELECTRON MICROSCOPY;

CHANNEL PROFILE DESIGN; GATE CURRENT; GATE LENGTH SCALING; OXYNITRIDE GATE DIELECTRIC; POLYSILICON DEPLETION; THERMAL BUDGET;

CMOS INTEGRATED CIRCUITS;

EID: 0035716657     PISSN: 01631918     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEDM.2001.979590     Document Type: Article

References (9)