Adaptive supply serial links with sub-1-V operation and per-pin clock recovery

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 11, 2002, Pages 1403-1413

  Kim, Jaeha ^a   Horowitz, Mark A ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Adaptive power supply regulation; Clock recovery phase delay locked loop (PLL DLL); High speed interfaces; Low power; Low voltage; Multiphase clock; Serial links

Indexed keywords

CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; TRANSCEIVERS;

ADAPTIVE POWER SUPPLY REGULATION; CLOCK RECOVERY PHASE; MULTIPHASE CLOCK;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036857082     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.803937     Document Type: Article

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