A scalable performance 32b microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 230-231

  Clark, L T ^a   Hoffman, E ^a   Schaecher, M ^a   Biyani, M ^a   Roberts, D ^a   Liao, Y ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CACHE MEMORY; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; REDUCED INSTRUCTION SET COMPUTING; STATIC RANDOM ACCESS STORAGE;

TRANSLATION LOOKASIDE BUFFERS (TLB);

MICROPROCESSOR CHIPS;

EID: 0035054822     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A high performance 180 nm generation logic technology
2. A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor