A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 396-397+470

  Wu, L ^a   Black W C , Jr ^a  

^a IOWA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CALIBRATION; CLOCKS; DELAY CIRCUITS; JITTER; OSCILLATORS (ELECTRONIC);

DELAY-LOCKED LOOPS (DLL); INTERLEAVING FUNCTIONS; MULTI-PHASE CLOCK GENERATORS;

PHASE LOCKED LOOPS;

EID: 0035061199     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Low jitter process-independent DLL and PLL based on self-biased techniques
2. PLL/DLL system noise analysis for low jitter clock synthesizer design
3. A digital background calibration technique for minimizing timing error effect in time-interleaved ADCs