A 2.75Gb/s CMOS clock recovery circuit with broad capture range

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 214-215+448

  Anand, S B ^a   Razavi, B ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTER SIMULATION; FREQUENCY DIVIDING CIRCUITS; INTEGRATED CIRCUIT LAYOUT; JITTER; OPTICAL COMMUNICATION; OPTICAL FIBERS; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS;

CLOCK RECOVERY CIRCUITS; VOLTAGE CONTROLLED OSCILLATORS (VCO);

CMOS INTEGRATED CIRCUITS;

EID: 0035054908     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A 52MHz and 155MHz clock - Recovery PLL
2. A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s
3. A 6.5GHz monolithic CMOS voltage-controlled oscillator
4. A 4-MHZ CMOS continuous-time filter with on-chip automatic tuning
5. A self correcting clock recovery circuit