Variable-frequency parallel I/O interface with adaptive power-supply regulation

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 11, 2000, Pages 1600-1610

  Wei, Gu Yeon ^a   Kim, Jaeha ^a,c   Liu, Dean ^a,d   Sidiropoulos, Stefanos ^b   Horowitz, Mark A ^a,b  

^a STANFORD UNIVERSITY   (United States)

^b RAMBUS INC   (United States)

^c Seoul National University   (South Korea)

^d UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC IMPEDANCE; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCIES; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SPURIOUS SIGNAL NOISE; SWITCHING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

ADAPTIVE POWER SUPPLY REGULATION; DC-DC POWER CONVERSION; DUAL LOOP DELAY LOCKED LOOP; HIGH FREQUENCY NOISE; INPUT OUTPUT SUBSYSTEM;

DIGITAL INTEGRATED CIRCUITS;

EID: 0034314916     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.881205     Document Type: Article

References (14)

1. P. Macken, M. Degrauwe, M. Van Paemel, and H. Oguey, "A voltage reduction technique for digital systems," in IEEE ISSCC Dig. Tech. Papers, Feb. 1990, pp. 238-239.
2. V. Gutnik and A. P. Chandrakasan, "An efficient controller for variable supply-voltage low power processing," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 1996, pp. 158-159.
3. T. Burd, T. Pering, A. Stratakos, and R. Broderson, "A dynamic voltage scaled microprocessor system," in IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp. 294-295.
4. K. Suzuki et al., "A 300-MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS," in IEEE Custom Integrated Circuits Conf., May 1997, pp. 587-590.
5. C. K. Yang et al., "A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling," IEEE J. Solid-State Circuits, vol. 33, pp. 713-722, May 1998.
6. S. Sidiropoulos and M. Horowitz, "A 700-Mb/s/pin CMOS signalling interface using current integrating receivers," IEEE J. Solid State Circuits, vol. 32, pp. 681-690, May 1997.
7. S. Sidiropoulos, D. Liu, J. Kim, G.-Y. Wei, and M. Horowitz, "Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers," in Proc. IEEE Symp. VLSI Circuits, June 2000, pp. 124-127.
8. G. Wei and M. Horowitz, "A fully digital energy efficient adaptive power-supply regulator," IEEE J. Solid-State Circuits, vol. 34, pp. 520-528, Apr. 1999.
9. A. P. Chandrakasan et al., "Data-driven signal processing: An approach for energy-efficient computing," in IEEE ISLPED, Aug. 1996, pp. 347-352.
10. E. Yeung and M. Horowitz, "A 2.4-Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation," in IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp. 256-257.
11. S. Sidiropoulos and M. Horowitz, "A semi-digital dual delay-locked loop," IEEE J. Solid-State Circuits, vol. 32, pp. 1683-1692, Nov. 1997.
12. J. Maneatis, "Low-jitter process independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 28, Dec. 1993.
13. B. Lau et al., "A 2.6-Gb/s multipurpose chip-to-chip interface," in IEEE ISSCC Dig. Tech. Papers, Feb. 1998, pp. 162-163.
14. M. Johnson, "Bias circuit and differential amplifier having stabilized output swing," U.S. Patent 5452898, Sept. 1995.