-
1
-
-
0028204653
-
Multifrequency zero-jitter delay-locked loop
-
Jan.
-
A. Efendovich, Y. Afek, C. Sella, and Z. Bikowsky, "Multifrequency zero-jitter delay-locked loop," IEEE J. Solid-Sate Circuits, vol. 29, pp. 67-70, Jan. 1994.
-
(1994)
IEEE J. Solid-Sate Circuits
, vol.29
, pp. 67-70
-
-
Efendovich, A.1
Afek, Y.2
Sella, C.3
Bikowsky, Z.4
-
2
-
-
0029717417
-
Skew minimization techniques for 256 Mb synchronous DRAM and beyond
-
June
-
J.-M. Han, J. Lee, S. Yoon, S. Jeong, C. Park, I. Cho, S. Lee, and D. Seo, "Skew minimization techniques for 256 Mb synchronous DRAM and beyond," in VLS Circuits Dig. Tech. Papers, June 1996, pp. 192-193.
-
(1996)
VLS Circuits Dig. Tech. Papers
, pp. 192-193
-
-
Han, J.-M.1
Lee, J.2
Yoon, S.3
Jeong, S.4
Park, C.5
Cho, I.6
Lee, S.7
Seo, D.8
-
3
-
-
0031072202
-
A 256 Mb SDRAM using register-controlled digital DLL
-
Feb.
-
A. Hatakeyama, H. Mochizuki, T. Aikawa, M. Takita, Y. Ishii, H. Tsuboi, S. Fujioka, S. Yamaguchi, M. Koga, Y. Serizawa, K. Nishimura, K. Kawabata, Y. Okajima, M. Kawano, H. Kojima, K. Mizutani, T. Anezaki, M. Hasegawa, and M. Taguchi, "A 256 Mb SDRAM using register-controlled digital DLL," in ISSCC 1997 Dig. Tech. Papers, Feb. 1997, pp. 72-73.
-
(1997)
ISSCC 1997 Dig. Tech. Papers
, pp. 72-73
-
-
Hatakeyama, A.1
Mochizuki, H.2
Aikawa, T.3
Takita, M.4
Ishii, Y.5
Tsuboi, H.6
Fujioka, S.7
Yamaguchi, S.8
Koga, M.9
Serizawa, Y.10
Nishimura, K.11
Kawabata, K.12
Okajima, Y.13
Kawano, M.14
Kojima, H.15
Mizutani, K.16
Anezaki, T.17
Hasegawa, M.18
Taguchi, M.19
-
4
-
-
0028757753
-
A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM
-
Dec.
-
T. Lee, K. Donnelly, J. Ho, J. Zerbe, M. Johnson, and T. Ishikawa, "A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM," IEEE J. Solid-State Circuits, vol. 29, pp. 1491-1496, Dec. 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, pp. 1491-1496
-
-
Lee, T.1
Donnelly, K.2
Ho, J.3
Zerbe, J.4
Johnson, M.5
Ishikawa, T.6
-
6
-
-
0030395335
-
A 660MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC
-
Dec.
-
K. Donnelly, Y. Chan, J. Ho, C. Tran, S. Patel, B. Lau, J. Kim, P. Chau, C. Huang, J. Wei, L. Yu, R. Tarver, R. Kulkarni, D. Stark, and M. Johnson, "A 660MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC," IEEE J. Solid-State Circuits, vol. 31, pp. 1995-2003, Dec. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 1995-2003
-
-
Donnelly, K.1
Chan, Y.2
Ho, J.3
Tran, C.4
Patel, S.5
Lau, B.6
Kim, J.7
Chau, P.8
Huang, C.9
Wei, J.10
Yu, L.11
Tarver, R.12
Kulkarni, R.13
Stark, D.14
Johnson, M.15
-
7
-
-
0027578956
-
A 500-Megabyte/s data-rate 4.5M DRAM
-
Apr.
-
N. Kushiyama, S. Ohshima, D. Stark, H. Noji, K. Sakurai, S. Takase, T. Furuyama, R. Barth, A. Chan, J. Dillon, J. Gasbarro, M. Griffin, M. Horowitz, T. Lee, and V. Lee, "A 500-Megabyte/s data-rate 4.5M DRAM," IEEE J. Solid-State Circuits, vol. 28, pp. 490-508, Apr. 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, pp. 490-508
-
-
Kushiyama, N.1
Ohshima, S.2
Stark, D.3
Noji, H.4
Sakurai, K.5
Takase, S.6
Furuyama, T.7
Barth, R.8
Chan, A.9
Dillon, J.10
Gasbarro, J.11
Griffin, M.12
Horowitz, M.13
Lee, T.14
Lee, V.15
-
8
-
-
0031678266
-
A 256 Mb SDRAM with subthreshold leakage current suppression
-
Feb.
-
M. Hasegawa, M. Nakamura, S. Narui, S. Ohkuma, Y. Kawase, H. Endoh, S. Miyatake, T. Akiba, K. Kawakita, M. Yoshida, S. Yamada, T. Sekigguchi, I. Asano, Y. Tadaki, R. Nagai, S. Miyaoka, K. Kajigaya, M. Horiguchi, and Y. Nakagome, "A 256 Mb SDRAM with subthreshold leakage current suppression," in ISSCC 1998 Dig. Tech. Papers, Feb. 1998, pp. 80-81.
-
(1998)
ISSCC 1998 Dig. Tech. Papers
, pp. 80-81
-
-
Hasegawa, M.1
Nakamura, M.2
Narui, S.3
Ohkuma, S.4
Kawase, Y.5
Endoh, H.6
Miyatake, S.7
Akiba, T.8
Kawakita, K.9
Yoshida, M.10
Yamada, S.11
Sekigguchi, T.12
Asano, I.13
Tadaki, Y.14
Nagai, R.15
Miyaoka, S.16
Kajigaya, K.17
Horiguchi, M.18
Nakagome, Y.19
-
9
-
-
0030083363
-
A 2.5 ns clock access 250 MHz 256 Mb SDRAM with synchronous mirror delay
-
Feb.
-
T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, E. Kakehashi, J. Drynan, M. Komuro, T. Fukase, H. Iwasaki, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, K. Yoshida, H. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, K. Koyama, Y. Fukuzo, and T. Okuda, "A 2.5 ns clock access 250 MHz 256 Mb SDRAM with synchronous mirror delay," ISSCC 1996 Dig. Tech. Papers, Feb. 1996, pp. 374-375.
-
(1996)
ISSCC 1996 Dig. Tech. Papers
, pp. 374-375
-
-
Saeki, T.1
Nakaoka, Y.2
Fujita, M.3
Tanaka, A.4
Nagata, K.5
Sakakibara, K.6
Matano, T.7
Hoshino, Y.8
Miyano, K.9
Isa, S.10
Kakehashi, E.11
Drynan, J.12
Komuro, M.13
Fukase, T.14
Iwasaki, H.15
Sekine, J.16
Igeta, M.17
Nakanishi, N.18
Itani, T.19
Yoshida, K.20
Yoshino, H.21
Hashimoto, S.22
Yoshii, T.23
Ichinose, M.24
Imura, T.25
Uziie, M.26
Koyama, K.27
Fukuzo, Y.28
Okuda, T.29
more..
-
10
-
-
0031617667
-
A portable digital DLL architecture for CMOS interface circuits
-
June
-
B. Garlepp, K. Donnelly, J. Kim, P. Chau, J. Zerbe, C. Huang, C. Tran, C. Portmann, D. Stark, Y. Chan, T. Lee, and M. Horowitz, "A portable digital DLL architecture for CMOS interface circuits," in VLSI Circuits Dig. Tech. Papers, June 1998, pp. 214-215.
-
(1998)
VLSI Circuits Dig. Tech. Papers
, pp. 214-215
-
-
Garlepp, B.1
Donnelly, K.2
Kim, J.3
Chau, P.4
Zerbe, J.5
Huang, C.6
Tran, C.7
Portmann, C.8
Stark, D.9
Chan, Y.10
Lee, T.11
Horowitz, M.12
-
11
-
-
0031651834
-
A process independent 800 MB/s DRAM bytewide interface featuring command interleaving and concurrent memory operation
-
Feb.
-
M. Griffin, J. Zerbe, A. Chan, Y. Jun, Y. Tanaka, W. Richardson, G. Tsang, M. Ching, C. Portmann, Y. Li, B. Stonecypher, L. Lai, K. Lee, V. Lee, D. Stark, H. Modarres, P. Batra, J. Louis-Chandran, J. Privitera, T. Thrush, B. Nickell, J. Yang, V. Hennon, and R. Sauve, "A process independent 800 MB/s DRAM bytewide interface featuring command interleaving and concurrent memory operation," in ISSCC 1998 Dig. Tech. Papers, Feb. 1998, pp. 156-157.
-
(1998)
ISSCC 1998 Dig. Tech. Papers
, pp. 156-157
-
-
Griffin, M.1
Zerbe, J.2
Chan, A.3
Jun, Y.4
Tanaka, Y.5
Richardson, W.6
Tsang, G.7
Ching, M.8
Portmann, C.9
Li, Y.10
Stonecypher, B.11
Lai, L.12
Lee, K.13
Lee, V.14
Stark, D.15
Modarres, H.16
Batra, P.17
Louis-Chandran, J.18
Privitera, J.19
Thrush, T.20
Nickell, B.21
Yang, J.22
Hennon, V.23
Sauve, R.24
more..
-
12
-
-
0037888395
-
-
Ph.D. dissertation, Computer Systems Laboratory, Stanford University, Stanford, CA, Apr. Available as Tech. Rep. CSL-TR-98-760
-
S. Sidiropoulos, "High-performance interchip signalling," Ph.D. dissertation, Computer Systems Laboratory, Stanford University, Stanford, CA, Apr. 1998. Available as Tech. Rep. CSL-TR-98-760 from http://elib.stanford.edu/.
-
(1998)
High-performance Interchip Signalling
-
-
Sidiropoulos, S.1
-
13
-
-
0031069283
-
A 0.35 μm CMOS 3-880 MHz PLL N/2 multiplier and distribution network with low jitter for microprocessors
-
Feb.
-
I. Young, M. Mar, and B. Bhushan, "A 0.35 μm CMOS 3-880 MHz PLL N/2 multiplier and distribution network with low jitter for microprocessors," in ISSCC 1997 Dig. Tech. Papers, Feb. 1997, pp. 330-331.
-
(1997)
ISSCC 1997 Dig. Tech. Papers
, pp. 330-331
-
-
Young, I.1
Mar, M.2
Bhushan, B.3
-
14
-
-
0030087135
-
A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation
-
Feb.
-
V. von Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra, "A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation," in ISSCC 1996 Dig. Tech. Papers, Feb. 1996, pp. 132-133.
-
(1996)
ISSCC 1996 Dig. Tech. Papers
, pp. 132-133
-
-
Von Kaenel, V.1
Aebischer, D.2
Piguet, C.3
Dijkstra, E.4
-
15
-
-
0031706879
-
A 600 MHz CMOS PLL microprocessor clock generator with a 1.2 GHz VCO
-
Feb.
-
V. von Kaenel, D. Aebischer, R. van Dongen, and C. Piguet, "A 600 MHz CMOS PLL microprocessor clock generator with a 1.2 GHz VCO," in ISSCC 1998 Dig. Tech. Papers, Feb. 1998, pp. 396-397.
-
(1998)
ISSCC 1998 Dig. Tech. Papers
, pp. 396-397
-
-
Von Kaenel, V.1
Aebischer, D.2
Van Dongen, R.3
Piguet, C.4
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