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Volumn 34, Issue 5, 1999, Pages 632-644

A portable digital DLL for high-speed CMOS interface circuits

Author keywords

Delay circuits; Delay locked loops (DLL's); Digital control; Digital DLL; Phase blending; Phase control; Phase synchronization

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; DIGITAL CONTROL SYSTEMS; INTERFACES (COMPUTER); PHASE CONTROL; SYNCHRONIZATION;

EID: 0032635505     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.760373     Document Type: Article
Times cited : (166)

References (15)
  • 12
    • 0037888395 scopus 로고    scopus 로고
    • Ph.D. dissertation, Computer Systems Laboratory, Stanford University, Stanford, CA, Apr. Available as Tech. Rep. CSL-TR-98-760
    • S. Sidiropoulos, "High-performance interchip signalling," Ph.D. dissertation, Computer Systems Laboratory, Stanford University, Stanford, CA, Apr. 1998. Available as Tech. Rep. CSL-TR-98-760 from http://elib.stanford.edu/.
    • (1998) High-performance Interchip Signalling
    • Sidiropoulos, S.1
  • 13
    • 0031069283 scopus 로고    scopus 로고
    • A 0.35 μm CMOS 3-880 MHz PLL N/2 multiplier and distribution network with low jitter for microprocessors
    • Feb.
    • I. Young, M. Mar, and B. Bhushan, "A 0.35 μm CMOS 3-880 MHz PLL N/2 multiplier and distribution network with low jitter for microprocessors," in ISSCC 1997 Dig. Tech. Papers, Feb. 1997, pp. 330-331.
    • (1997) ISSCC 1997 Dig. Tech. Papers , pp. 330-331
    • Young, I.1    Mar, M.2    Bhushan, B.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.