A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 6, 2001, Pages 910-916

  Sun, Lizhong ^b   Kwasniewski, Tadeusz A ^a,c  

^a IEEE

^b LUCENT TECHNOLOGIES   (United States)

^c CARLETON UNIVERSITY   (Canada)

Author keywords

Analog integrated circuits; Clock generation; Frequency synthesizer; Phase locked loop

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; PHASE LOCKED LOOPS;

ANALOG INTEGRATED CIRCUITS; CLOCK GENERATION; MULTIPHASE RING OSCILLATOR; SUBFEEDBACK LOOP;

VARIABLE FREQUENCY OSCILLATORS;

EID: 0035368885     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.924853     Document Type: Article

References (13)

1. A 30-MHz hybrid analog-digital clock recovery circuit in 2-μm CMOS
2. NMOS ICs for clock and data regeneration in gigabit-per-second optical-fiber receivers
3. A gigahertz voltage-controlled ring oscillator
4. Precise delay generation using coupled oscillators
5. A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme
6. CMOS current controlled oscillators using multiple feedback loop ring architectures
7. A quadrature output voltage-controlled ring oscillator based on three-stage subfeedback loops
8. Design of monolithic phase-locked loops and clock recovery circuits-A tutorial
9. Low-jitter process-independent DLL and PLL based on self-biased techniques
10. A variable delay line PLL for CPU-coprocessor synchronization
11. High-speed CMOS circuit technique
12. A 1.25-GHz 0.35-μm monolithic CMOS PLL clock generator for data communications