A monolithic 50-200 MHz CMOS clock recovery and retiming circuit

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1989, Pages

  Baumert, R J ^a   Metz, P C ^a   Pedersen, M E ^a   Pritchett, R L ^a   Young, J A ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK RECOVERY; DIGITAL CMOS TECHNOLOGY; PSEUDO RANDOM; RANDOM DATA; REFERENCE CLOCK; RETIMING; SINGLE-ENDED;

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS;

CLOCKS;

EID: 0011902269     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.1989.56754     Document Type: Conference Paper

References (6)

1. C.W.Leung,et.al., A High Performance Submicron Twin Tub V Technology for Custom VLSI Applications, Custom Integrated Circuits Conference Digest, May 1988, pp 25.1.1-25.1.4.
2. Fairchild Semiconductor Corporation, P100K ECL User's Handbook, 1986.
3. R.L.Pritchett, Alok Gupta, RJ.Baumert, D.J.Hart, A Monolithic I to 50 MHz CMOS Clock Recovery and Retiming Chip, European Solid-State Circuits Conference, September 1986 digest pp. 122-124
4. M.E.Pedersen, P.C.Metz, A CMOS to WOK ECL I/O Interface Circuit, I.E.E.E. International Solid-State Circuits Conference, February 1989 digest
5. H.S.Moscovitz.et.aL, Automatic Full-Custom Design of Application Specific DSP VLSI, I.E.E.E. International Symposium on Circuits and Systems digest 1988, pp 577-580.
6. R.Y.Tsui,et.al., A Three Layer Router for Standard Cell VLSI Circuits, I.E.E.E. International Symposium on Circuits and Systems digest 1988, pp 1441-1444.