Adaptive supply serial links with sub-1 V operation and per-pin clock recovery

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 268-269+466+263

  Kim, Jaeha ^a   Horowitz, Mark A ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; ELECTRIC LOADS; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; MOSFET DEVICES; MULTIPLEXING; PHASE LOCKED LOOPS; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS;

DELAY-LOCKED LOOPS (DLL);

POWER SUPPLY CIRCUITS;

EID: 0036116897     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Low-power area-efficient high-speed I/O circuit techniques
2. A variable-frequency parallel I/O interface with adaptive power supply regulation
3. An efficient digital sliding controller for adaptive power supply regulation
4. A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links
5. A 700 Mbps/pin CMOS signalling interface using current integrating receivers
6. A semidigital dual delay-locked loop