A 1.3 Cycle lock time, non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for "clock on demand"

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 166-167

  Saeki, T ^a   Mitsuishi, M ^a   Iwaki, H ^a   Tagishi, M ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; ERROR ANALYSIS; FEEDBACK CONTROL; FREQUENCY DOUBLERS; GATES (TRANSISTOR); INTERPOLATION; PHASE LOCKED LOOPS; PHASE MEASUREMENT; WAVEFORM ANALYSIS;

MULTIPHASE CLOCK MULTIPLIERS (MPM); SHORT-CIRCUIT-CURRENT-SUPPRESSION (SCCS);

TIMING CIRCUITS;

EID: 0034429720     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Clock buffer chip with absolute delay regulation over process and environmental variations
2. A 10ps jitter 2 clock cycle time CMOS digital clock generator based on an interleaved synchronous mirror delay scheme
3. A jitter and data duty distortion toretated PLL circuit for 156Mb/s Burst-Mode transmission
4. A potable clock multiplier generator using digital CMOS standard cells
5. A portable digital DLL for high-speed CMOS interface circuits
6. Matching properties of MOS transistors