A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 12, 1996, Pages 2015-2023

  Yang, Chih Kong Ken ^a,b,c   Horowitz, Mark A ^a  

^a Stanford University   (United States)

^b STANFORD UNIVERSITY   (United States)

^c Tau Beta Pi ^*

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; FREQUENCY DIVISION MULTIPLEXING; PHASE LOCKED LOOPS; RADIO TRANSMITTERS; TELECOMMUNICATION LINKS;

MULTIPLE PHASE CLOCKS;

TRANSCEIVERS;

EID: 0030400848     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.545825     Document Type: Article

References (6)

1. S. Kim et al., "An 800 Mbps multi-channel CMOS serial link with 3× oversampling," in IEEE 1995 Custom Integrated Circuits Conf. Proc., Feb. 1995, p. 451.
2. A. Yukawa, "A CMOS 8-bit high-speed A/D converter IC," IEEE J. Solid-State Circuits, vol. 20, no. 3, pp. 775-779, June 1985.
3. Motorola MECL Device Data, 3rd ed. Motorola, Inc., pp. 6-81-6-84, 1979.
4. I. Novof et al., "Fully integrated CMOS phase-locked loop with 15-240 MHz locking range and ±50 ps jitter," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 112-113.
5. J. Maneatis and M. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273-1282, Dec. 1993.
6. N. Kushiyama et al., "A 500-Megabytes/s data-rate 4.5M DRAM," IEEE J. Solid-State Circuits, vol. 28, pp. 490-498, Apr. 1993.