An eight channel 36Gsample/s CMOS timing analyzer

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 170-171

  Weinlader, D ^a   Ho, R ^a   Chih Kong Ken Yang, ^a   Horowitz, M ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); PHASE LOCKED LOOPS; PHASE MEASUREMENT; SAMPLED DATA CONTROL SYSTEMS; SOLID STATE OSCILLATORS; SPURIOUS SIGNAL NOISE; TIMING JITTER;

DELAY-LOCKED LOOP (DLL) CLOCK GENERATORS; TIMING ANALYZERS;

TIMING CIRCUITS;

EID: 0034429728     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Low-jitter process-independent DLL and PLL based on self-biased techniques
2. Precise delay generation using coupled oscillators
3. A 500MHz time digitizer IC with 15.625ps resolution