2.5GHz 4-phase clock generator with scalable and no feedback loop architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 398-399+470

  Yamguchi, K ^a   Fukaishi, M ^a   Sakamoto, T ^a   Akiyama, N ^a   Nakamura, K ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; TWO TERM CONTROL SYSTEMS; WAVEFORM ANALYSIS;

DELAY COMPENSATION TECHNIQUES; MULTI-PHASE CLOCKING; QUADRATURE-CLOCK GENERATORS (QCG);

PHASE LOCKED LOOPS;

EID: 0035058939     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A 90mW 4Gb/s equalized I/O circuit with input offset cancellation
2. A CMOS 50% duty cycle repeater using complementary phase blending
3. A semidigital dual delay-locked loop
4. A 1.3 cycle lock time non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for clock on demand