A novel reconfigurable wrapper for testing of embedded core-based SOCs and its associated scheduling algorithm

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 4-5, 2002, Pages 415-434

  Koranne, Sandeep ^a  

^a Tanner Research Inc   (United States)

Author keywords

Embedded core based test scheduling; Parallel scheduling of malleable tasks; Reconfigurable wrapper; System on chip test; VLSI test

Indexed keywords

ALGORITHMS; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; SEMICONDUCTING SILICON; TIME DOMAIN ANALYSIS; VECTOR QUANTIZATION;

ASSOCIATED SCHEDULING ALGORITHM; EMBEDDED CORE; RECONFIGURABLE WRAPPER; SYSTEM ON CHIP TEST; TEST ACCESS MECHANISM;

INTEGRATED CIRCUIT TESTING;

EID: 0036694332     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1016593423844     Document Type: Article

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