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Volumn , Issue , 2000, Pages 432-437
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Design of system-on-a-chip test access architectures under place-and-route and power constraints
a
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Author keywords
[No Author keywords available]
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Indexed keywords
COMBINATORIAL CIRCUITS;
COMPUTER ARCHITECTURE;
CONSTRAINT THEORY;
DESIGN FOR TESTABILITY;
ELECTRIC POWER SUPPLIES TO APPARATUS;
INTEGER PROGRAMMING;
LINEAR PROGRAMMING;
MICROPROCESSOR CHIPS;
SEQUENTIAL CIRCUITS;
PLACE AND ROUTE CONSTRAINTS;
SYSTEM-ON-A-CHIP DESIGN;
TEST ACCESS MECHANISMS;
LOGIC DESIGN;
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EID: 0033683901
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/337292.337531 Document Type: Conference Paper |
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Times cited : (70)
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References (14)
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