Useless memory allocation in system-on-a-chip test: Problems and solutions

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 423-429

  Gonciari, P T ^a   Al Hashimi, B M ^a   Nicolici, N ^b  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^b MCMASTER UNIVERSITY   (Canada)

Author keywords

Algorithm design and analysis; Automatic test equipment; Automatic testing; Circuit testing; Design for testability; Integrated circuit testing; Partitioning algorithms; Semiconductor device manufacture; System testing; System on a chip

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATIC TESTING; DESIGN; DESIGN FOR TESTABILITY; ELECTRIC NETWORK ANALYSIS; EQUIPMENT TESTING; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; MEMORY ARCHITECTURE; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; SYSTEM-ON-CHIP; VLSI CIRCUITS;

ALGORITHM DESIGN AND ANALYSIS; AUTOMATIC TEST EQUIPMENT; CIRCUIT TESTING; PARTITIONING ALGORITHMS; SYSTEM ON A CHIP; SYSTEM TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 84893789144     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011175     Document Type: Conference Paper

References (22)

1. J. Aerts and E. J. Marinissen. Scan Chain Design for Test Time Reduction in Core-Based ICs. In Proceedings IEEE International Test Conference (ITC), pages 448-457, 1998.
2. C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, B. Keller, and B. Koenemann. OPMISR: The Fundation for Compressed ATPG Vectors. In Proceedings IEEE International Test Conference (ITC), pages 738-747, 2001.
3. J. Bedsole, R. Raina, A. Crouch, and M. S. Abadir. VeryLow Cost Testers: Opportunities and Challenges. IEEE Design & Test of Computers, 18(5):60-69, Sept. 2001.
4. B. Bottoms. The third millennium's test dilemma. IEEE Design & Test of Computers, 15(4):7-11, Oct. 1998.
5. F. Brglez, D. Bryan, and K. Kozminski. Combinational profiles of sequential benchmark circuits. In Proceedings International Symposium on Circuits and Systems (ISCAS), pages 1929-1934, 1989.
6. M. L. Bushnell and V. D. Agrawal. Esentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. 2000.
7. K. Chakrabarty. Design of System-on-a-Chip Test Access Architectures Using Integer Linear Programming. In Proceedings IEEE VLSI Test Symposium (VTS), pages 127-134, 2000.
8. A. Chandra and K. Chakrabarty. System-on-a-Chip Test Data Compression and Decompression Architectures Based on Golomb Codes. IEEE Transactions on Computer-Aided Design, 20:113-120, Mar. 2001.
9. I. Ghosh, S. Dey, and N. K. Jha. A Fast and Low Cost Testing Technique for Core-based System-on-Chip. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 542-547, 1998.
10. F. F. Hsu, K. M. Butler, and J. H. Patel. A Case Studyon the Implementation of the Illinois Scan Architecture. In Proceedings IEEE International Test Conference (ITC), pages 538-547, 2001.
11. V. Immaneni and S. Raman. Direct Access Test Scheme - Design of Block and Core Cells for Embedded ASICs. In Proceedings IEEE International Test Conference (ITC), pages 488-492, 1990.
12. V. Iyengar, K. Chakrabarty, and E. J. Marinissen. Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores. In Proceedings IEEE International Test Conference (ITC), pages 1023-1032, 2001.
13. A. Jas and N. Touba. Test Vector Decompression Via Cyclical Scan Chains and Its Application to Testing Core-Based Designs. In Proceedings IEEE International Test Conference (ITC), pages 458-464, 1998.
14. E. J. Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, and C. Wouters. A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores. In Proceedings IEEE International Test Conference (ITC), pages 284-293, 1998.
15. E. J. Marinissen, S. K. Goel, and M. Lousberg. Wrapper Design for Embedded Core Test. In Proceedings IEEE International Test Conference (ITC), pages 911-921, 2000.
16. E. J. Marinissen, R. Kapur, and Y. Zorian. On Using IEEE P1500 SECT for Test Plug-n-Play. In Proceedings IEEE International Test Conference (ITC), pages 770-777, 2000.
17. M. Nourani and C. Papachristou. An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing. In Proceedings IEEE International Test Conference (ITC), pages 902-910, 2000.
18. A. Sivaram. Split Timing Mode (STM) - Answer to Dual Frequency Domain Testing. In Proceedings IEEE International Test Conference (ITC), pages 140-147, 2001.
19. N. Touba and B. Pouya. Testing Embedded Cores Using Partial Isolation Rings. In Proceedings IEEE VLSI Test Symposium (VTS), pages 10-16, 1997.
20. P. Varma and S. Bhatia. A Structured Test Re-Use Methodology for Core-Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 294-302, 1998.
21. B. West and T. Napier. Sequencer per pin™ test system architecture. In Proceedings IEEE International Test Conference (ITC), pages 355-361, 1990.
22. Y. Zorian, S. Dey, and M. Rodgers. Test of future system-on-chips. In Proceedings International Conference on Computer-Aided Design (ICCAD), pages 392-398, 2000.