To optimize electrical properties of the ultrathin (1.6 nm) nitride/oxide gate stacks with bottom oxide materials and post-deposition treatment

IEEE Transactions on Electron Devices

Volumn 48, Issue 12, 2001, Pages 2769-2776

  Chen, Chein Hao ^a   Fang, Yean Kuen ^a   Yang, Chih Wei ^a   Ting, Shyh Fann ^a   Tsair, Yong Shiuan ^a   Wang, Ming Fang ^b   Hou, Tuo Hong ^b   Yu, Mo Chiun ^b   Chen, Shih Chang ^b   Jang, Simon M ^b   Yu, Douglas C H ^b   Liang, Mong Song ^b  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Bottom oxide; N2O; NH3; Nitride oxide (N O); Post deposition annealing; Ultrathin

Indexed keywords

ANNEALING; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; ELECTRON MOBILITY; LEAKAGE CURRENTS; MOSFET DEVICES; SEMICONDUCTOR DOPING; ULTRATHIN FILMS;

RAPID THERMAL CHEMICAL VAPOR DEPOSITION (RTCVD);

ULSI CIRCUITS;

EID: 0035696645     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.974702     Document Type: Article

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