The performance and reliability of PMOSFET's with ultrathin silicon nitride/oxide stacked gate dielectrics with nitrided Si-SiO 2 interfaces prepared by remote plasma enhanced CVD and post-deposition rapid thermal annealing

IEEE Transactions on Electron Devices

Volumn 47, Issue 7, 2000, Pages 1361-1369

  Wu, Yider ^a,b   Lucovsky, Gerald ^a,b   Lee, Yi Mu ^b  

^a IEEE   (United States)

^b North Carolina State University   (United States)

Author keywords

Boron penetration; Gate dielectrics; N O; Nitride; Oxide

Indexed keywords

BORON PENETRATION; GATE DIELECTRICS; REMOTE PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION;

CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); INTERFACES (MATERIALS); NITRIDES; OXIDES; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; RAPID THERMAL ANNEALING; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTING SILICON COMPOUNDS; THRESHOLD VOLTAGE; ULTRATHIN FILMS;

MOSFET DEVICES;

EID: 0034227480     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.848278     Document Type: Article

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