1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O) composites prepared by RPECVD/oxidation process

IEEE Electron Device Letters

Volumn 21, Issue 3, 2000, Pages 116-118

  Wu, Yider ^a   Lee, Yi Mu ^b   Lucovsky, Gerald ^b  

^a ADVANCED MICRO DEVICES   (United States)

^b North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPOSITE MATERIALS; DIELECTRIC FILMS; ELECTRIC CURRENTS; GATES (TRANSISTOR); INTERFACES (MATERIALS); MOSFET DEVICES; NITRIDES; OXIDATION; OXIDES; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SEMICONDUCTOR GROWTH;

GATE DIELECTRICS; PLASMA GROWN OXIDE INTERFACE LAYERS; QUANTUM EFFECT; TUNNELING CURRENT;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0033872334     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.823574     Document Type: Article

References (12)

1. Y. Wu and G. Lucovsky, "Ultrathin nitride/oxide (N/O) gate dielectrics for p+-poly gated PMOSFET's prepared by a combined remote plasma enhanced CVD/thermal oxidation process," IEEE Electron Device Lett., vol. 19, p. 367, 1998.
2. -, "Improvement of gate dielectric reliability for p+ poly MOS devices using remote PECVD top nitride deposition on thin gate oxides." in IEEE Int.Reliability Physics Symp., 1998, p. 70.
3. -, "Improvement of gate dielectric reliability for p+ poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4-6 nm) gate oxides," Microelectron. Reliab., vol. 39, p. 365, 1999.
4. C. Parker, G. Lucovsky, and J. Hauser. "Ultrathin oxide-nitride gate dielectric MOSFET's" IEEE Electron Device Lett., vol. 19, p. 106, 1998.
5. G. Lucovsky et al., "Bonding constraint and defect formation at interfaces between crystalline silicon and advanced single layer and composite gate dielectrics," Appl. Phys. Lett., vol. 74, p. 2005, 1999.
6. H. Niimi, H. Yang, and G. Lucovsky, "A new low thermal budget approach to interface nitridation for ultra-thin silicon dioxide gate dielectrics by combined plasma-assisted and rapid thermal processing." in Proc. Int. Conf. Characterization and Metrology for VLSI Technology, 1998, p. 273.
7. S. Hattangady, H. Niimi, and G. Lucovsky. "Controlled nitrogen incorporation at the gate oxide surface," Appl. Phys. Lett., vol. 66, p. 3495. 1995.
8. C. Chang, "General formalism for quantitative Auger analysis." Surf. Sci., vol. 48, p. 9, 1975.
9. Y. Ma, T. Yasuda, and G. Lucovsky, "Ultrathin device quality oxide-nitride-oxide heretostructure formed by remote plasma enhanced chemical vapor deposition." Appl. Phys. Lett., vol. 64, p. 2226, 1994.
10. W. Henson et al., "Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors," IEEE Electron Device Lett., vol. 20, p. 179, 1999.
11. S. Lo, D. Buchanan, Y. Taur, and W. Wang, "Quantum-mechanical modeling of electron tunneling current from inversion layer of ultra-thinoxide nMOSFET's," IEEE Electron Device Lett., vol. 18, p. 209, 1997.
12. J. Hauser, "Extraction of experimental mobility data for MOS devices," IEEE Trans. Electron Devices, vol. 43, p. 1981, 1996.