Effect of polysilicon gate type on the flatband voltage shift for ultrathin oxide-nitride gate stacks

IEEE Electron Device Letters

Volumn 21, Issue 4, 2000, Pages 170-172

  Wang, Zhigang ^a   Parker, Chris G ^a   Hodge, Dexter W ^a   Croswell, Robert T ^a   Yang, Nian ^a   Misra, Veena ^a   Hauser, John R ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; FERMI LEVEL; GATES (TRANSISTOR); INTERFACES (MATERIALS); NITROGEN OXIDES; OXIDATION; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING; SILICA; SILICON NITRIDE; SUBSTRATES;

CAPACITANCE VOLTAGE CURVES; EQUIVALENT OXIDE THICKNESS; FLATBAND VOLTAGE; OXIDE NITRIDE; POLYSILICON GATE; REMOTE PLASMA OXIDATION;

MOSFET DEVICES;

EID: 0033877012     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.830971     Document Type: Article

References (8)

1. V. Misra et al., "Interfacial properties of ultrathin pure silicon nitride formed by remote plasma enhanced chemical vapor deposition," J. Vac. Sci. Technol. B, vol. 17, pp. 1836-1839, July/Aug. 1999.
2. J. Schmidt and A. G. Aberle, "Carrier recombination at silicon-silicon nitride interfaces fabricated by plasma-enhanced chemical vapor deposition," J. Appl. Phys., vol. 85, pp. 3626-3633, Apr. 1, 1999.
3. J. Schmidt et al., "Observation of multiple defect states at silicon-silicon nitride interfaces fabricated by low-frequency plasma-enhanced chemical vapor deposition," Appl. Phys. Lett., pp. 252-254, July 1997.
4. + polysilicon gated PMOSFET's prepared by a combined remote plasma enhanced CVD/thermal oxidation process," IEEE Electron Device Lett., vol. 19, pp. 367-369, Oct. 1998.
5. C. G. Parker, G. Lucovsky, and J. R. Hauser, "Ultrathin oxide-nitride gate dielectric MOSFET's," IEEE Electron Device Lett., vol. 19, pp. 106-108, Apr. 1998.
6. Y. Ma et al., "Ultra-thin oxide/nitride stacked gate dielectric formed with remote plasma enhanced chemical vapor deposition," presented at the Proc. Electrochem. Soc. 195th Meeting, Seattle, WA, May 2-6, 1999.
7. A. Usami, M. Ando, M. Tsunekane, and T. Wada, "Shallow-junction formation on silicon by rapid thermal diffusion of impurities from a spin-on source," IEEE Trans. Electron Devices, vol. 39, pp. 105-110, Jan. 1992.
8. J. R. Hauser and K. Ahmed et al., "Characterization of ultrathin oxides using electrical C-V and I-V measurements," in AIP Conf. Proc. 449: Characterization and Metrology for ULSI Technology, D. G. Seiler et al., Eds., 1998, pp. 235-239.