Methods for evaluating and covering the design space during early design development

Integration, the VLSI Journal

Volumn 38, Issue 2, 2004, Pages 131-183

  Gries, Matthias ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Benchmarking; Design frameworks; Design space exploration; Design space pruning; Micro architecture design; Multi objective search; System level design

Indexed keywords

ALGORITHMS; BENCHMARKING; CLASSIFICATION (OF INFORMATION); COMPUTER HARDWARE; COMPUTER SOFTWARE; EMBEDDED SYSTEMS; HIERARCHICAL SYSTEMS; SYSTEMS ANALYSIS;

DESIGN FRAMEWORKS; DESIGN SPACE EXPLORATION; DESIGN SPACE PRUNING; MICRO-ARCHITECTURE DESIGN; MULTI-OBJECTIVE SEARCH; SYSTEM-LEVEL DESIGN;

VLSI CIRCUITS;

EID: 9644281035     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(04)00032-X     Document Type: Review

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