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Volumn 19, Issue 6, 2002, Pages 6-16

Developing architectural platforms: A disciplined approach

Author keywords

[No Author keywords available]

Indexed keywords


EID: 0036857174     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2002.1047739     Document Type: Article
Times cited : (22)

References (12)
  • 2
    • 0011819177 scopus 로고    scopus 로고
    • The Trimedia VLIW media processor
    • In-Stat/MDR, Scottsdale, Ariz.
    • K. Vissers, "The Trimedia VLIW Media Processor," Proc. Embedded Processor Forum, In-Stat/MDR, Scottsdale, Ariz., 2001.
    • (2001) Proc. Embedded Processor Forum
    • Vissers, K.1
  • 3
    • 0035311949 scopus 로고    scopus 로고
    • Embedded computer architecture and automation
    • Apr.
    • B. Rau and M. Schlansker, "Embedded Computer Architecture and Automation," Computer, vol. 34, no. 4, Apr. 2001, pp. 75-83.
    • (2001) Computer , vol.34 , Issue.4 , pp. 75-83
    • Rau, B.1    Schlansker, M.2
  • 4
    • 0003703503 scopus 로고    scopus 로고
    • master's thesis, Dept. of Electrical Eng. and Computer Sciences, Univ. of Calif., Berkeley
    • N. Shah, "Understanding Network Processors," master's thesis, Dept. of Electrical Eng. and Computer Sciences, Univ. of Calif., Berkeley, 2001.
    • (2001) Understanding Network Processors
    • Shah, N.1
  • 5
    • 0003628955 scopus 로고    scopus 로고
    • tech. report UCB/ERL M99/40, Dept. of Electrical Eng. and Computer Sciences, Univ. of Calif., Berkeley
    • J. Davis et al., "Ptolemy II: Heterogeneous Concurrent Modeling and Design in Java," tech. report UCB/ERL M99/40, Dept. of Electrical Eng. and Computer Sciences, Univ. of Calif., Berkeley, 1999.
    • (1999) Ptolemy II: Heterogeneous Concurrent Modeling and Design in Java
    • Davis, J.1
  • 6
    • 79952781954 scopus 로고    scopus 로고
    • A benchmarking methodology for network processors
    • (HPCA 02), IEEE CS Press, Los Alamitos, Calif.
    • M. Tsai et al., "A Benchmarking Methodology for Network Processors," Proc. 8th Int'l Symp. High-Performance Computer Architectures (HPCA 02), IEEE CS Press, Los Alamitos, Calif., 2002, pp. 75-85.
    • (2002) Proc. 8th Int'l Symp. High-Performance Computer Architectures , pp. 75-85
    • Tsai, M.1
  • 8
    • 0030679033 scopus 로고    scopus 로고
    • An approach for quantitative analysis of application-specific dataflow architectures
    • IEEE CS Press, Los Alamitos, Calif.
    • B. Kienhuis et al., "An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures," Proc. Int'l Conf. Application-Specific Systems, Architectures, and Processors (ASAP 97), IEEE CS Press, Los Alamitos, Calif., 1997, pp. 338-349.
    • (1997) Proc. Int'l Conf. Application-Specific Systems, Architectures, and Processors (ASAP 97) , pp. 338-349
    • Kienhuis, B.1
  • 9
    • 85056381767 scopus 로고    scopus 로고
    • Architecture description languages for retargetable compilation
    • Y.N. Srikant and P. Shankar, eds., CRC Press, Boca Raton, Fla.
    • W. Qin and S. Malik, "Architecture Description Languages for Retargetable Compilation," The Compiler Design Handbook: Optimizations and Machine Code Generation, Y.N. Srikant and P. Shankar, eds., CRC Press, Boca Raton, Fla., 2002.
    • (2002) The Compiler Design Handbook: Optimizations and Machine Code Generation
    • Qin, W.1    Malik, S.2
  • 11
    • 0034846659 scopus 로고    scopus 로고
    • Addressing the system-on-a-chip interconnect woes through communication-based design
    • IEEE CS Press, Los Alamitos, Calif.
    • M. Sgroi et al., "Addressing the System-on-a-Chip Interconnect Woes through Communication-Based Design," Proc. Design Automation Conf. (DAC 01 ), IEEE CS Press, Los Alamitos, Calif., 2001, pp. 667-672.
    • (2001) Proc. Design Automation Conf. (DAC 01 ) , pp. 667-672
    • Sgroi, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.