Performance analysis of systems with multi-channel communication architectures

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2000, Pages 530-537

  Lahiri, Kanishka ^a   Raghunathan, Anand ^a   Dey, Sujit ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; GRAPH THEORY; INTEGRATED CIRCUIT MANUFACTURE; NETWORK PROTOCOLS; PERFORMANCE; SYSTEMS ANALYSIS;

COMMUNICATION ANALYSIS GRAPH; MULTI CHANNEL COMMUNICATION ARCHITECTURE; SYSTEM ON CHIP INTEGRATED CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033886663     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)