Programmable stream processors

Computer

Volumn 36, Issue 8, 2003, Pages 54-62

  Kapasi, Ujval J ^a   Rixner, Scott ^b   Dally, William J ^a   Khailany, Brucek ^a   Ahn, Jung Ho ^a   Mattson, Peter ^d   Owens, John D ^c  

^a STANFORD UNIVERSITY   (United States)

^b RICE UNIVERSITY   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d NONE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; DIGITAL ARITHMETIC; IMAGE COMPRESSION; MULTIMEDIA SYSTEMS; REQUIREMENTS ENGINEERING; SIGNAL PROCESSING; THREE DIMENSIONAL COMPUTER GRAPHICS; VLSI CIRCUITS;

ARITHMETIC LOGIC UNIT; LOCAL REGISTER FILES; PROGRAMMABLE STREAM PROCESSORS; STREAM REGISTER FILES;

PROGRAM PROCESSORS;

EID: 0041562664     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2003.1220582     Document Type: Article

References (8)

1. S.D. Naffziger et al., "The Implementation of the Itanium 2 Microprocessor," IEEE J. Solid-State Circuits, Nov. 2002, pp. 1448-1460.
2. W. Thies, M. Karczmarek, and S. Amarasinghe, "StreamIt: A Language for Streaming Applications," Proc. 11th Int'l Conf. Compiler Construction, LNCS 2304, Springer-Verlag, 2002, pp. 179-196.
3. U.J. Kapasi et al., Stream Scheduling, Concurrent VLSI Architecture Tech. Report 122, Computer Systems Laboratory, Stanford Univ., Stanford, Calif., 2002.
4. S. Rixner et al., "A Bandwidth-Efficient Architecture for Media Processing," Proc. 31st Ann. ACM/IEEE Int'l Symp. Microarchitecture, IEEE CS Press, 1998, pp. 3-13.
5. D. Sager et al., "A 0.18μm CMOS IA32 Microprocessor with a 4-GHz Integer Execution Unit," 2001 IEEE Int'l Solid-State Circuits Conf. Digest of Technical Papers, IEEE Standards Office, 2001, pp. 324-325.
6. Texas Instruments, TMS320C6713 Floating-Point Digital Signal Processor, Datasheet SPRS186D, Dec. 2001, rev. May 2003; http://focus.ti.com/lit/ds/symlink/tms320c6713.pdf
7. B. Khailany et al., "Exploring the VLSI Scalability of Stream Processors," Proc. 9th Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, 2003, pp. 153-164.
8. W.J. Dally, P. Hanrahan, and R. Fedkiw, A Streaming Supercomputer, white paper, Computer Systems Laboratory, Stanford Univ., Stanford, Calif., 2001.