Efficiently searching the optimal design space

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1999, Pages 192-195

  Blythe, Stephen A ^a   Walker, Robert A ^a  

^a SAINT LOUIS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; CONSTRAINT THEORY; DIGITAL CIRCUITS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; PARETO PRINCIPLE;

HIGH LEVEL SYNTHESIS SYSTEM; OPTIMAL DESIGN SPACE; TIME CONSTRAINED SCHEDULING;

VLSI CIRCUITS;

EID: 0033361534     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)