Dynamically adaptive I-cache partitioning for energy-efficient embedded multitasking

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 11, 2011, Pages 2067-2080

  Paul, Mathew ^a   Petrov, Peter ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Adaptive cache partitioning; embedded multitasking; low power cache architectures

Indexed keywords

BUFFER STORAGE; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; LEAKAGE CURRENTS; MEMORY ARCHITECTURE; MULTITASKING;

BATTERY POWERED DEVICES; CACHE PARTITIONING; DYNAMIC POWER REDUCTION; LOW POWER CACHE; MODERN EMBEDDED SYSTEMS; PERFORMANCE REQUIREMENTS; PREEMPTIVE MULTITASKING; RESOURCE UTILIZATIONS;

CACHE MEMORY;

EID: 85027929285     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2066995     Document Type: Article

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