A Way-Halting Cache for Low-Energy High-Performance Systems

ACM Transactions on Architecture and Code Optimization

Volumn 2, Issue 1, 2005, Pages 34-54

  Zhang, Chuanjun ^a   Vahid, Frank ^b   Yang, Jun ^b   Najjar, Walid ^b  

^a UTC Aerospace Systems   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Cache; Design; Dynamic; Embedded systems; Experimentation; Low energy; Low power; Optimization; Performance

Indexed keywords

EID: 84996712396     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1061267.1061270     Document Type: Article

References (37)

1. Advanced Micro Devices. http://www.amd.com.
2. Albonesi, D. H. 2000. Selective cache ways: On-demand cache resource allocation. Journal of Instruction Level Parallelism.
3. Amrutur, B. and Horowitz, M. 1998. A replica technique for word line and sense control in low-power SRAM's. IEEE Journal of Solid-State Circuits 33, 8, 1208-1218.
4. Batson, B. and Vijaykumar, T. N. 2000. Reactive-associative caches. In International Conference on Parallel Architectures and Compilation Techniques.
5. Burger, D. and Austin, T. M. 1997. The SimpleScalar tool set, version 2.0. University of Wisconsin-Madison Computer Sciences Dept., Technical Report #1342.
6. CADENCE. http://www.cadence.com.
7. Calder, B., Grunwall, D., and Emer, J. 1996. Predictive sequential associative cache. In International Symposium on High Performance Computer Architecture.
8. Ckelov, M. and Dubois, M. 1997. Virtual-address caches. Part 1: Problems and Solutions in Uniprocessors. IEEE Micro 17, 5, 64-71.
9. Edmondson, J. H. and Rubinfield, P. I. 1995. Internal organization of the Alpha 21164 a 300-MHz 64-bit quad-issue CMOS RISC microprocessor. Digital Technical Journal 7, 1, 119-135.
10. Efthymiou, A. and Garside, J. D. 2002. An adaptive serial-parallel CAM architecture for low-power cache blocks. In Proceedings of the International Symposium on Low Power Electronics and Design.
11. Furber, S. B., Efthymiou, A., Garside, J. D., Lloyd, D. W., Lewis, M. J. G., and Temple, S. 2001. Power management in the Amulet microprocessors. IEEE Design & Test of Computers 18, 2, 42-52.
12. Garside, J. D., Temple, S., and Mehra, R. 1996. The AMULET2e cache system. In 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems.
13. Hasegawa, A., Kawasaki, I., Yamada, K., Yoshioka, S., Kawasaki, S., and Biswas, P. 1995. SH3: High code density, low power. IEEE Micro, Dec.
14. Hennessy, J. L. and Patterson, D. A. 2002. Computer Architecture: A Quantitative Approach, 3rd ed., International Student Edition. Morgan Kaufman, San Mateo, CA.
15. Huang, M., Renau, J., Yoo, S. M., and Torrellas, J. 2001. L1 data cache decomposition for energy efficiency. In International Symposium on Low Power Electronics and Design.
16. IBM. http://www.ibm.com.
17. Inoue, K., Ishihara, T., and Murakami, K. 1999. Way-predictive set-associative cache for high performance and low energy consumption. in International Symposium on Low Power Electronics and Design.
18. Juan, Lang, T., and Navarro, J. 1996. The difference-bit cache. In Proceedings of the 27th Annual International Symposium on Computer Architecture.
19. Lee, C., Potkonjak, M., and Mangione-Smith, W. 1997. MediaBench: A tool for evaluating and synthesizing multimedia and communications systems. in International Symposium on Microarchitecture.
20. Liu, L. 1994. Cache design with partial address matching. In Proceedings of the 27th Annual International Symposium on Microarchitecture.
21. Malik, A., Moyer, B., and Cermak, D. 2000. A low power unified cache architecture providing power and poerformance flexibility. In International Symposium on Low Power Electronics and Design.
22. MIPS Technologies, Inc. http://www.mips.com.
23. Montanaro, J., Witek, R. T., Anne, K., Black, A. J., Cooper, E. M., Dobberpuhl, D. W., Donahue, P. M., Eno, J., Farell, A., Hoeppner, G. W., Kruckemyer, D., Lee, T. H., Lin, P., Madden, L., Murray, D., Pearce, M., Santhanam, S., Snyder, K. J., Stephany, R., and Thierauf, S. C. 1996. A 160 MHz 32 b 0.5 W CMOS RISC microprocessor. In IEEE International Solid-State Circuits Conference.
24. The Mosis Service. http://www.mosis.org.
25. Petrov, P. and Orailoglu, A. 2001. Data cache energy minimizations through programmable tag size matching to the applications. In International Symposium on System Synthesis.
26. Powell, M., Agarwal, A., Vijaykumar, T. N., Falsafi, B. and Roy, K. 2001. Reducing set-associative cache energy via way-prediction and selective direct-mapping. In International Symposium on Microarchitecture.
27. Panwar, R. and Rennels, D. 1995. Reducing the frequency of tag compares for low power I-cache design. In SLPE, pp. 57-62.
28. Reinmann, G. and Jouppi, N. P. 1999. CACTI2.0: An Integrated Cache Timing and Power Model. COMPAQ Western Research Lab.
29. Santhanam, S., et al. 1998. A low-cost, 300-MHz, RISC CPU with attached media processor. IEEE Journal of Solid-State Circuits 33, 11.
30. Segars, S. 2000. Low power design techniques for microprocessors. In International Solid-State Circuits Conference Tutorial.
31. Taylor, G., Davis, P., and Farmwald, M. 1990. The TLB slice-A low-cost high-speed address translation mechanisms. In Proceedings of the 17th Annual International Symposium on Computer Architecture.
32. Witchel, E., Larsen, S., Ananian, C. S., and Asanovic, K. 2001. Direct addressed caches for reduced power consumption. In International Symposium on Microarchitecture.
33. Yang, J. and Gupta, R. 2002. Energy efficient frequent value data cache design. In International Symposium on Microarchitecture.
34. Zhang, C., Vahid, F., Yang, J., and Najjar, W. 2004. A way-halting cache for low-energy high performance systems. In International Symposium on Low Power Electronics and Design.
35. Zhang, C. Vahid, F., and Najjar, W. 2003. A highly-configurable cache architecture for embedded systems. In International Symposium on Computer Architecture.
36. Zhang, C. Vahid, F., and Najjar, W. 2005. A highly-configurable cache architecture for embedded systems. ACM Transactions on Embedded Computing Systems.
37. Zhang, M. and Asanovic, K. 2000. Highly-associative caches for low-power processors. In Kool Chips Workshop, in conjunction with International Symposium on Microarchitecture.