Thread-associative memory for multicore and multithreaded computing

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2006, Issue , 2006, Pages 139-142

  Wang, Shuo ^a   Wang, Lei ^a  

^a UNIVERSITY OF CONNECTICUT   (United States)

Author keywords

Cache mapping; Memory system; Multicore; Multithreading

Indexed keywords

CACHE MAPPING; MEMORY SYSTEMS; MULTICORE; MULTITHREADING;

BUFFER STORAGE; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS;

ASSOCIATIVE STORAGE;

EID: 34247272420     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1165573.1165606     Document Type: Conference Paper

References (13)

1. D. M. Tullsen, S. J. Eggers, and H. M. Levy, "Simultaneous multithreading: Maximizing on-chip parallelism," Proc. Intl. Symp. Computer Architecture., pp. 392-403, Jun. 1995.
2. J. L. Lo, et al., "Converting Thread-Level Parallelism Into Instruction-Level Parallelism via Simultaneous Multithreading," ACM Trans. on Computer Systems, pp. 322-354, Aug. 1997.
3. K. Olukotun et al., "The Case for a Single Chip Multiprocessor," Proc. 7th Intl. Conf. Architectural, Support for Programming Languages and Operating Systems, ACM Press, New York, pp. 2-11, 1996.
4. L. Hammond, B. Nayfeh, and K. Olukotun, "A Single-Chip Multiprocessor," Computer, vol. 30, no. 9, pp. 79-85, Sept. 1997.
5. D. Chandra., et al., "Predicting inter-thread cache contention on a chip multi-processor architecture," Proc. Intl. Syrnp. on High Performance Computer Architecture, pp. 340-351, Feb. 2005.
6. G. E. Suh, L. Rudolph, and S. Devadas, "Dynamic partitioning of shared cache memory," The Journal of Supercomputing, pp. 7-26, Apr. 2004.
7. A. Settle, et al., "A Dynamically Reconfigurable Cache for Multithreaded Processors," The Journal of Embedded Computing (JEC), special issue, Dec. 2005.
8. S. J. Eggers, et al., "Simultaneous multithreading: A platform for next-generation processors," IEEE Micro, pp. 12-19, 1997.
9. C. Zhang, and F. Vahid, "A self-tuning cache architecture for embedded systems," Design, Automation and Test Conference in Europe, pp. 142-147, 2004.
10. C. Zhang, et al., "A way-halting cache for low-energy high-performance systems," Low Power Electronics and Design, pp. 126-131, Aug. 2004.
11. J. Edler and M. D. Hill, "Dinero IV Trace-Driven Uniprocessor Cache Simulator," at http://www.cs.wise.edu/~markhill/DineroIV/,2006.
12. SPEC CPU2000 at http://www.spec.org/cpu/.
13. A. Milenkovic and M. Milenkovic, "Exploiting Streams in Instruction and Data Address Trace Compression," Proceedings of the IEEE 6th Annual Workshop on Workload Characterization, pp. 99-107, Oct. 2003.