Reducing Instruction Cache Energy Consumption Using a Compiler-Based Strategy

ACM Transactions on Architecture and Code Optimization

Volumn 1, Issue 1, 2004, Pages 3-33

  Zhang, W ^a   Hu, J S ^b   Degalahal, V ^b   Kandemir, M ^b   Vijaykrishnan, N ^b   Irwin, M J ^b  

^a Southern Illinois University   (United States)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Cache design; Compiler optimizations; Design; Leakage power; Performance; Reliability

Indexed keywords

EID: 84987658048     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/980152.980154     Document Type: Article

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