Fast context switching by hierarchical task allocation and reconfigurable cache

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Volumn 2003-January, Issue , 2003, Pages 20-29

  Tanaka, Kiyofumi ^a,b  

^a JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; MEMORY ARCHITECTURE; MULTITASKING; PIPELINE PROCESSING SYSTEMS; PIPELINES; RECONFIGURABLE ARCHITECTURES; SWITCHING;

CONTEXT SWITCHING; MEMORY ACCESS LATENCY; MULTIPLE CONTEXTS; MULTITASKING ENVIRONMENTS; MULTITHREADED PROCESSORS; REAL-TIME APPLICATION; REALTIME PROCESSING; RISC PROCESSORS;

REDUCED INSTRUCTION SET COMPUTING;

EID: 84945587523     PISSN: 15373223     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWIA.2003.1262779     Document Type: Conference Paper

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