A low power front-end for embedded processors using a block-aware instruction set

CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Volumn , Issue , 2007, Pages 267-276

  Zmily, Ahmad ^a   Kozyrakis, Christos ^a  

^a Stanford University   (United States)

Author keywords

Instruction prefetching; Instruction re ordering; Low power front end; Software hints; Tagless instruction cache; Unified instruction cache and BTB

Indexed keywords

CACHE MEMORY; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

INSTRUCTION PREFETCHING; INSTRUCTION RE-ORDERING; LOW POWER FRONT-END; SOFTWARE HINTS; TAGLESS INSTRUCTION CACHE;

PROGRAM PROCESSORS;

EID: 38849094450     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1289881.1289926     Document Type: Conference Paper

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