Performance analysis of the memory management unit under scale-out workloads

IISWC 2014 - IEEE International Symposium on Workload Characterization

Volumn , Issue , 2014, Pages 1-12

  Karakostas, Vasileios ^a,b   Unsal, Osman S ^b   Nemirovsky, Mario ^a   Cristal, Adrian ^a,b   Swift, Michael ^c  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; PHYSICAL ADDRESSES;

APPLICATION DATA; APPLICATION PERFORMANCE; CACHE HIERARCHIES; HARDWARE SUPPORTS; PERFORMANCE ANALYSIS; PERFORMANCE COUNTERS; PERFORMANCE GAPS; UPPER BOUND;

MEMORY MANAGEMENT UNITS;

EID: 84946036877     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IISWC.2014.6983034     Document Type: Conference Paper

References (49)

1. "Cloudsuite Overview," http://parsa.epfl.ch/cloudsuite/overview.html.
2. "Huge Pages Part 1 (Introduction)," http://lwn.net/Articles/374424/.
3. "International Technology Roadmap for Semiconductors: 2012," http://www.itrs.net/Links/2012ITRS/Home2012.htm.
4. "Perf wiki," https://perf.wiki.kernel.org/index.php/Main Page.
5. "SPEC CPU 2006," https://www.spec.org/cpu2006/.
6. "The/proc filesystem," www.kernel.org/doc/Documentation/filesystems/proc.txt.
7. "Transparent Huge Pages in 2.6.38," http://lwn.net/Articles/423584/.
8. K. Albayraktaroglu, A. Jaleel, X. Wu, M. Franklin, B. Jacob, C.-W. Tseng, and D. Yeung, "BioBench: A Benchmark Suite of Bioinformatics Applications," ISPASS, 2005, pp. 2-9.
9. T. E. Anderson, H. M. Levy, B. N. Bershad, and E. D. Lazowska, "The interaction of architecture and operating system design," ASPLOS, 1991, pp. 108-120.
10. V. Babka and P. Tuma, "Investigating Cache Parameters of x86 Family Processors," SPEC Benchmark Workshop on Computer Performance Evaluation and Benchmarking, 2009, pp. 77-96.
11. T. W. Barr, A. L. Cox, and S. Rixner, "Translation Caching: Skip, Don't Walk (the Page Table)," ISCA, 2010, pp. 48-59.
12. L. A. Barroso, J. Clidaras, and U. Hlzle, The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines, Second Edition, ser. Synthesis Lectures on Computer Architecture, 2013.
13. A. Basu, J. Gandhi, J. Chang, M. D. Hill, and M. M. Swift, "Efficient Virtual Memory for Big Memory Servers," ISCA, 2013, pp. 237-248.
14. A. Basu, M. D. Hill, and M. M. Swift, "Reducing memory reference energy with opportunistic virtual caching," ISCA, 2012, pp. 297-308.
15. A. Bhattacharjee, "Large-reach Memory Management Unit Caches," MICRO, 2013, pp. 383-394.
16. A. Bhattacharjee and M. Martonosi, "Inter-core Cooperative TLB for Chip Multiprocessors," ASPLOS, 2010, pp. 359-370.
17. A. Bhattacharjee and M. Martonosi, "Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors," PACT, 2009, pp. 29-40.
18. C. Bienia, "Benchmarking Modern Multiprocessors," Ph.D. dissertation, Princeton University, January 2011.
19. M. Cekleov and M. Dubois, "Virtual-address caches part 1: Problems and solutions in uniprocessors," IEEE Micro, vol. 17, no. 5, pp. 64-71, Sep. 1997.
20. M. Cekleov and M. Dubois, "Virtual-address caches, part 2: Multiprocessor issues," IEEE Micro, vol. 17, no. 6, pp. 69-74, Nov. 1997.
21. J. B. Chen, A. Borg, and N. P. Jouppi, "A Simulation Based Study of TLB Performance," ISCA, 1992, pp. 114-123.
22. Y.-T. Chen, J. Cong, H. Huang, B. Liu, C. Liu, M. Potkonjak, and G. Reinman, "Dynamically Reconfigurable Hybrid Cache: An Energyefficient Last-level Cache Design," DATE, 2012, pp. 45-50.
23. D. W. Clark and J. S. Emer, "Performance of the VAX-11/780 translation buffer: simulation and measurement," ACM Trans. Comput. Syst., vol. 3, no. 1, pp. 31-62, Feb. 1985.
24. C. Dougan, P. Mackerras, and V. Yodaiken, "Optimizing the Idle Task and Other MMU Tricks," OSDI, 1999, pp. 229-237.
25. M. Ferdman, A. Adileh, O. Kocberber, S. Volos, M. Alisafaee, D. Jevdjic, C. Kaynak, A. D. Popescu, A. Ailamaki, and B. Falsafi, "Clearing the Clouds: A Study of Emerging Scale-out Workloads on Modern Hardware," ASPLOS, 2012, pp. 37-48.
26. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 3rd ed., 2002.
27. Intel Corporation, IntelR 64 and IA-32 Architectures Optimization Reference Manual, April 2012, no. 248966-026.
28. B. L. Jacob and T. N. Mudge, "A Look at Several Memory Management Units, TLB-refill Mechanisms, and Page Table Organizations," ASPLOS, 1998, pp. 295-306.
29. D. Jevdjic, S. Volos, and B. Falsafi, "Die-stacked DRAM Caches for Servers: Hit Ratio, Latency, or Bandwidth? Have It All with Footprint Cache," ISCA, 2013, pp. 404-415.
30. Z. Jia, L. Wang, J. Zhan, L. Zhang, and C. Luo, "Characterizing Data Analysis Workloads in Data Centers," IISWC, 2013, pp. 66-76.
31. G. B. Kandiraju and A. Sivasubramaniam, "Going the distance for TLB prefetching: an application-driven study," ISCA, 2002, pp. 195-206.
32. G. B. Kandiraju and A. Sivasubramaniam, "Characterizing the d-TLB Behavior of SPEC CPU2000 Benchmarks," SIGMETRICS, 2002, pp. 129-139.
33. S. Kaxiras and A. Ros, "A new perspective for efficient virtual-cache coherence," ISCA, 2013, pp. 535-546.
34. K. Lim, D. Meisner, A. G. Saidi, P. Ranganathan, and T. F. Wenisch, "Thin servers with smart pipes: designing SoC accelerators for memcached," ISCA, 2013, pp. 36-47.
35. P. Lotfi-Kamran, B. Grot, and B. Falsafi, "NOC-Out: Microarchitecting a Scale-Out Processor," MICRO, 2012, pp. 177-187.
36. P. Lotfi-Kamran, B. Grot, M. Ferdman, S. Volos, O. Kocberber, J. Picorel, A. Adileh, D. Jevdjic, S. Idgunji, E. Ozer, and B. Falsafi, "Scaleout processors," ISCA, 2012, pp. 500-511.
37. D. Lustig, A. Bhattacharjee, and M. Martonosi, "TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs," ACM Trans. Archit. Code Optim., vol. 10, no. 1, pp. 2:1-2:38, Apr. 2013.
38. C. McCurdy, A. L. Cox, and J. Vetter, "Investigating the TLB Behavior of High-end Scientific Applications on Commodity Microprocessors," ISPASS, 2008, pp. 95-104.
39. A. Morari, R. Gioiosa, R. W. Wisniewski, B. S. Rosenburg, T. Inglett, and M. Valero, "Evaluating the Impact of TLB Misses on Future HPC Systems," IPDPS, 2012, pp. 1010-1021.
40. D. Nagle, R. Uhlig, T. Stanley, S. Sechrest, T. Mudge, and R. Brown, "Design tradeoffs for software-managed TLBs," ISCA, 1993, pp. 27-38.
41. B. Pham, A. Bhattacharjee, Y. Eckert, and G. H. Loh, "Increasing TLB reach by exploiting clustering in page translations." HPCA, 2014, pp. 558-567.
42. B. Pham, V. Vaidyanathan, A. Jaleel, and A. Bhattacharjee, "CoLT: Coalesced Large-Reach TLBs," MICRO, 2012, pp. 258-269.
43. X. Qiu and M. Dubois, "Towards Virtually-Addressed Memory Hierarchies," HPCA, 2001, pp. 51-62.
44. M. Rosenblum, E. Bugnion, S. A. Herrod, E. Witchel, and A. Gupta, "The Impact of Architectural Trends on Operating System Performance," SOSP, 1995, pp. 285-298.
45. A. Saulsbury, F. Dahlgren, and P. Stenstr, "Recency-based TLB Preloading," ISCA, 2000, pp. 117-127.
46. M. Talluri and M. D. Hill, "Surpassing the TLB Performance of Superpages with Less Operating System Support," ASPLOS, 1994, pp. 171-182.
47. D. A. Wood, S. J. Eggers, G. Gibson, M. D. Hill, and J. M. Pendleton, "An In-cache Address Translation Mechanism," ISCA, 1986, pp. 358-365.
48. C.-J. Wu and M. Martonosi, "Characterization and dynamic mitigation of intra-application cache interference," ISPASS, 2011, pp. 2-11.
49. W. Xu, H. Sun, X. Wang, Y. Chen, and T. Zhang, "Design of Last-level On-chip Cache Using Spin-torque Transfer RAM (STT RAM)," IEEE Trans. Very Large Scale Integr. Syst., vol. 19, no. 3, pp. 483-493, Mar. 2011.