Inter-core cooperative TLB prefetchers for chip multiprocessors

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2010, Pages 359-370

  Bhattacharjee, Abhishek ^a   Martonosi, Margaret ^a  

^a Princeton University   (United States)

Author keywords

Parallelism; Prefetching; Translation lookaside buffer

Indexed keywords

CHIP MULTIPROCESSOR; CORE CORRELATION; HARDWARE AND SOFTWARE IMPLEMENTATIONS; HARDWARE IMPLEMENTATIONS; HARDWARE/SOFTWARE; MISS-RATE; MODERN PROCESSORS; PERFORMANCE IMPROVEMENTS; PREFETCHING; TRANSLATION LOOKASIDE BUFFER; UNIPROCESSORS;

COMPUTER OPERATING SYSTEMS; HARDWARE; JAVA PROGRAMMING LANGUAGE; LINGUISTICS; MULTIPROCESSING SYSTEMS; QUERY LANGUAGES; SYSTEMS ANALYSIS; TRANSLATION (LANGUAGES);

BUFFER STORAGE;

EID: 77952252973     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1736020.1736060     Document Type: Conference Paper

References (24)

1. T. Anderson et al. The Interaction of Architecture and Operating System Design. Intl. Symp. on Architecture Support for Programming Languages and Operating Systems, 1991.
2. A. Bhattacharjee and M. Martonosi. Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors. Intl. Conf. on Parallel Architectures and Compilation Techniques, 2009.
3. C. Bienia et al. The PARSEC Benchmark Suite: Characterization and Architectural Implications. Intl. Conf. on Parallel Architectures and Compilation Techniques, 2008.
4. J. B. Chen, A. Borg, and N. Jouppi. A Simulation Based Study of TLB Performance. Intl. Symp. on Computer Architecture, 1992.
5. T. Chen and J. Baer. Effective Hardware-based Data Prefetching for High-Performance Processors. IEEE Trans. on Computers, 1995.
6. D. Clark and J. Emer. Performance of the VAX-11/780 Translation Buffers: Simulation and Measurement. ACM Transactions on Computer Systems, 3(1), 1985.
7. F. Dahlgren, M. Dubois, and P. Stenström. Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. Intl. Conf. on Parallel Processing, 1993.
8. H. Huck and H. Hays. Architectural Support for Translation Table Management in Large Address Space Machines. Intl. Symp. on Computer Architecture, 1993.
9. B. Jacob and T. Mudge. Software-Managed Address Translation. Intl. Symp. on High Performance Computer Architecture, 1997.
10. B. Jacob and T. Mudge. A Look at Several Memory Management Units: TLB-Refill, and Page Table Organizations. Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, 1998.
11. B. Jacob and T. Mudge. Virtual Memory in Contemporary Microprocessors. IEEE Micro, 1998.
12. D. Joseph and D. Grunwald. Prefetching using Markov Predictors. Intl. Symp. on Computer Architecture, 1997.
13. G. Kandiraju and A. Sivasubramaniam. Characterizing the d-TLB Behavior of SPEC CPU2000 Benchmarks. ACM SIGMETRICS Intl. Conf. on Measurement and Modeling of Computer Systems, 2002.
14. G. Kandiraju and A. Sivasubramaniam. Going the Distance for TLB Prefetching: An Application-Driven Study. Intl. Symp. on Computer Architecture, 2002.
15. M. Martin et al. Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset. Comp. Arch. News, 2005.
16. D. Nagle et al. Design Tradeoffs for Software Managed TLBs. Intl. Symp. on Computer Architecture, 1993.
17. X. Qui and M. Dubois. Options for Dynamic Address Translations in COMAs. Intl. Symp. on Comp. Arch., 1998.
18. M. Rosenblum et al. The Impact of Architectural Trends on Operating System Performance. ACM Transactions on Modeling and Computer Simulation, 1995.
19. A. Saulsbury, F. Dahlgren, and P. Stenström. Recency-Based TLB Preloading. Intl. Symp. on Comp. Arch., 2000.
20. V. Srinivasan, E. Davidson, and G. Tyson. A Prefetch Taxonomy. IEEE Transaction on Computers, 53(2), 2004.
21. Sun. UltraSPARC III Cu User's Manual. 2004.
22. M. Talluri. Use of Superpages and Subblocking in the Address Translation Hierarchy. PhD Thesis, Dept. of CS, Univ. of Wisc., 1995.
23. M. Talluri and M. Hill. Surpassing the TLB Performance of Superpages with Less Operating System Support. Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, 1994.
24. Virtutech. Simics for Multicore Software. 2007.