Characterizing the TLB behavior of emerging parallelworkloads on chip multiprocessors

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2009, Pages 29-40

  Bhattacharjee, Abhishek ^a   Martonosi, Margaret ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSORS; COMPUTER INDUSTRY; MISS-RATE; MODERN COMPUTER SYSTEMS; MULTIPLE THREADS; ON-CHIP MULTIPROCESSOR; PARALLEL APPLICATION; PARALLEL EXECUTIONS; SIGNIFICANT IMPACTS; STREAM PATTERNS; SYSTEM CHARACTERIZATION; TRANSLATION LOOKASIDE BUFFER; UNIPROCESSORS;

MACHINE DESIGN; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PARALLEL ARCHITECTURES; SYSTEMS ANALYSIS;

BUFFER STORAGE;

EID: 70449652917     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2009.26     Document Type: Conference Paper

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