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Volumn 5419 LNCS, Issue , 2009, Pages 77-96

Investigating cache parameters of x86 Family processors

Author keywords

[No Author keywords available]

Indexed keywords

CACHE PARAMETERS; EXCELLENT PERFORMANCE; MEMORY ARCHITECTURE; PERFORMANCE ENGINEERING;

EID: 67650706769     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-93799-9_5     Document Type: Conference Paper
Times cited : (29)

References (14)
  • 1
    • 67650692240 scopus 로고    scopus 로고
    • Intel 64 and IA-32 Architectures software developer manual
    • Intel Corporation,Order Nr. 253668-027 and 253669-027,July
    • Intel Corporation: Intel 64 and IA-32 Architectures Software Developer Manual, Volume 3: System Programming, Order Nr. 253668-027 and 253669-254027 (July 2008)
    • (2008) Volume3: System Programming
  • 8
    • 67650680312 scopus 로고    scopus 로고
    • Intel 64 and IA-32 Architectures application note
    • Intel Corporation,Order No., April
    • Intel Corporation: Intel 64 and IA-32 Architectures Application Note: TLBs, Paging-Structure Caches, and Their Invalidation, Order Nr. 317080-318002 (April 2008)
    • (2008) TLBs, Paging-Structure Caches, and Their Invalidation , pp. 317080-318002
  • 10
    • 33244459867 scopus 로고    scopus 로고
    • Automatic measurement of memory hierarchy parameters
    • DOI 10.1145/1064212.1064233, SIGMETRICS 2005: International Conference on Measurement and Modeling of Computer Systems - Proceedings
    • Yotov, K., Pingali, K., Stodghill, P.: Automatic measurement of memory hierarchy parameters. In: Proceedings of the 2005 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, pp. 181-192. ACM, New York (2005) (Pubitemid 43275420)
    • (2005) Performance Evaluation Review , vol.33 , Issue.1 , pp. 181-192
    • Yotov, K.1    Pingali, K.2    Stodghill, P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.