Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 45-50

  Chen, Yu Ting ^a   Cong, Jason ^a   Huang, Hui ^a   Liu, Bin ^a   Liu, Chunyue ^a   Potkonjak, Miodrag ^a   Reinman, Glenn ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE ARCHITECTURE; CACHE DESIGN; CACHE SYSTEMS; CIRCUIT DESIGNS; ENERGY EFFICIENT; HIGH DENSITY; LOW LEAKAGE; NON-VOLATILE MEMORIES; ON-THE-FLY; PHASE-CHANGE RAM; SPIN TORQUE;

BENCHMARKING; DESIGN; ENERGY EFFICIENCY; EXHIBITIONS;

RECONFIGURABLE ARCHITECTURES;

EID: 84862110045     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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