Large-reach memory management unit caches

MICRO 2013 - Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

Volumn , Issue , 2013, Pages 383-394

  Bhattacharjee, Abhishek ^a  

^a RUTGERS UNIVERSITY   (United States)

Author keywords

memory management units; translation lookaside buffers; virtual memory

Indexed keywords

ADDRESS TRANSLATION; HARDWARE SUPPORTS; IMPROVE PERFORMANCE; MEASUREMENT STUDY; MODERN PROCESSORS; SOFTWARE/HARDWARE; TRANSLATION LOOKASIDE BUFFER; VIRTUAL MEMORY;

BUFFER STORAGE; COMPUTER ARCHITECTURE; FLOCCULATION; HARDWARE; OPTIMIZATION; PROGRAM COMPILERS;

MEMORY MANAGEMENT UNITS;

EID: 84892513543     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2540708.2540741     Document Type: Conference Paper

References (36)

1. Andrea Arcangeli, "Transparent Hugepage Support," KVM Forum, 2010.
2. T. Barr, A. Cox, and S. Rixner, "Translation Caching: Skip, Don't Walk (the Page Table)," ISCA, 2010.
3. -, "SpecTLB: A Mechanism for Speculative Address Translation," ISCA, 2011.
4. A. Basu, J. Gandhi, J. Chang, M. Swift, and M. Hill, "Efficient Virtual Memory for Big Memory Servers," ISCA, 2013.
5. R. Bhargava et al., "Accelerating Two-Dimensional Page Walks for Virtualized Systems," ASPLOS, 2008.
6. A. Bhattacharjee, D. Lustig, and M. Martonosi, "Shared Last-Level TLBs for Chip Multiprocessors," HPCA, 2010.
7. A. Bhattacharjee and M. Martonosi, "Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors," PACT, 2009.
8. -, "Inter-Core Cooperative TLB Prefetchers for Chip Multiprocessors," ASPLOS, 2010.
9. C. Bienia et al., "The PARSEC Benchmark Suite: Characterization and Architectural Implications," PACT, 2008.
10. D. Clark and J. Emer, "Performance of the VAX-11/780 Translation Buffers: Simulation and Measurement," ACM Transactions on Computer Systems, vol. 3, no. 1, 1985.
11. A. Clements, F. Kaashoek, and N. Zeldovich, "Scalable Address Spaces Using RCU Balanced Trees," ASPLOS, 2012.
12. M. Ferdman et al., "Clearing the Clouds: A Study of Emerging Scale-Out Workloads on Modern Hardware," ASPLOS, 2012.
13. M. Ferdman, C. Kaynak, and B. Falsafi, "Proactive Instruction Fetch," MICRO, 2011.
14. Intel Corporation, "TLBs, Paging-Structure Caches and their Invalidation," Intel Technical Report, 2008.
15. -, "Intel Developer's Manual," 2012.
16. A. Jaleel, "Memory Characterization of Workloads Using Instrumentation-Driven Simulation - A Pin-based Memory Characterization of the SPEC CPU2000 and SPEC CPU2006 Benchmark Suites," VSSAD Technical Report, 2007.
17. A. Jaleel, M. Mattina, and B. Jacob, "Last Level Cache (LLC) Performance of Data Mining Workloads on a CMP - A Case Study of Parallel Bioinformatics Workloads," International Symposium on High Performance Computer Architecture, 2006.
18. G. Kandiraju and A. Sivasubramaniam, "Going the Distance for TLB Prefetching: An Application-Driven Study," ISCA, 2002.
19. C. Kim, D. Burger, and S. Keckler, "NUCA: A Non-Uniform Cache Architecture for Wire-Delay Dominated On-Chip Caches," IEEE Micro Top Picks, 2003.
20. P. Lofti-Kamran et al., "Scale-Out Processors," ISCA, 2012.
21. G. Loh and M. Hill, "Efficiently Enabling Conventional Block Sizes for Very Large Die-Stacked DRAM Caches," MICRO, 2011.
22. N. Muralimanohar, R. Balasubramonian, and N. Jouppi, "CACTI 6.0: A Tool to Model Large Caches," Micro, 2007.
23. D. Nagle et al., "Design Tradeoffs for Software-Managed TLBs," ISCA, 1993.
24. J. Navarro et al., "Practical, Transparent Operating System Support for Superpages," OSDI, 2002.
25. B. Pham, V. Vaidyanathan, A. Jaleel, and A. Bhattacharjee, "CoLT: Coalesced Large Reach TLBs," MICRO, 2012.
26. M. Qureshi and G. Loh, "Fundamental Latency Tradeoffs in Architecting DRAM Caches," MICRO, 2012.
27. T. Romer et al., "Reducing TLB and Memory Overhead Using Online Superpage Promotion," ISCA, 1995.
28. M. Rosenblum et al., "The Impact of Architectural Trends on Operating System Performance," SOSP, 1995.
29. P. Rosenfield, E. Cooper-Balis, and B. Jacob, "DRAMSim2: A Cycle Accurate Memory System Simulator," IEEE Computer Architecture Letters, 2011.
30. A. Saulsbury, F. Dahlgren, and P. Stenström, "Recency-Based TLB Preloading," ISCA, 2000.
31. S. Somogyi et al., "Spatio-Temporal Memory Streaming," ISCA, 2009.
32. M. Talluri and M. Hill, "Surpassing the TLB Performance of Superpages with Less Operating System Support," ASPLOS, 1994.
33. M. Talluri, M. Hill, and Y. Khalidi, "A New Page Table for 64-bit Address Spaces," SOSP, 1995.
34. Vlastimil Babka and Petr Tuma, "Investigating Cache Parameters of x86 Processors," SPEC Benchmark Workshop, 2009.
35. C.-J. Wu et al., "PACman: Prefetch-Aware Cache Management for High Performance Caching," MICRO, 2011.
36. L. Wu, R. Barker, M. Kim, and K. Ross, "Navigating Big Data with High-Throughput, Energy-Efficient Data Partitioning," ISCA, 2013.