An introduction to reconfigurable systems

Proceedings of the IEEE

Volumn 103, Issue 3, 2015, Pages 291-317

  Lyke, James C ^a   Christodoulou, Christos G ^b   Vera, G Alonzo ^b   Edwards, Arthur H ^a  

^a AIR FORCE RESEARCH LABORATORY   (United States)

^b MSC01 1070   (United States)

Author keywords

Computer architecture; field programmable analog arrays; field programmable gate arrays; integrated circuit packaging; memory; metamaterials; microelectromechanicalsystem; microfluidics; microwave circuits; neural networks; photonics; programmable circuits; reconfigurable architectures; reconfigurable logic; routing; software defined networking; software radio; switching circuits

Indexed keywords

APPLICATION PROGRAMS; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES; METAMATERIALS; MICROFLUIDICS; MICROWAVE CIRCUITS; NETWORK ARCHITECTURE; NEURAL NETWORKS; PHOTONICS; RECONFIGURABLE ARCHITECTURES; SIGNAL RECEIVERS; SOFTWARE DEFINED NETWORKING; SOFTWARE RADIO; SWITCHING CIRCUITS;

FIELD PROGRAMMABLE ANALOG ARRAY; INTEGRATED CIRCUIT PACKAGING; MICROELECTROMECHANICALSYSTEM; PROGRAMMABLE CIRCUITS; RECONFIGURABLE LOGIC; ROUTING;

RECONFIGURABLE HARDWARE;

EID: 84928318767     PISSN: 00189219     EISSN: 15582256     Source Type: Journal    
DOI: 10.1109/JPROC.2015.2397832     Document Type: Article

References (224)

1. J. Cameron and W. Wisher, Jr., Terminator 2: Judgment Day, 1991, (motion picture).
2. E. Ackerman, "A thousand kilobots self-Assemble into complex shapes, " IEEE Spectrum, Aug. 14, 2014. [Online]. Available: http://spectrum.ieee.org/automaton/robotics/robotics-hardware/a-thousandkilobots-self-Assemble.
3. A. Emmerson, " Strowger and the invention of the automatic telephone exchange, 1879-1912," Inst. Elect. Eng. Discussion Meeting 'Milestones in Telecommunications' and Lecture 'The Life and Works of A H Reeves', pp. 1-8, Nov. 23, 1989.
4. J. von Neumann, First Draft of a Report on the EDVAC, Contract No. W-670-ORD-4926 (between the United States Army Ordinance Department and the University of Pennsylvania Moore School of Electrical Engineering, University of Pennsylvania), Jun. 30, 1945
5. A. M. Turing and B. J. Copeland, Eds., The Essential Turing: Seminal Writings in Computing, Logic, Philosophy, Artificial Intelligence, Artificial Life, Plus the Secrets of Enigma. 1 st ed. New York, NY, USA: Oxford Univ., 2004.
6. I. Kuon and J. J. Rose, "Measuring the gap between FPGAs and ASICs, " IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 2, pp. 203-215, Feb. 2007.
7. G. E. Moore, "Cramming more components onto integrated circuits, " Electronics, vol. 38, no. 8, pp. 114-117, Apr. 19, 1965.
8. J. Mitola, "The software radio architecture, " IEEE Commun. Mag., vol. 33, no. 5, pp. 26-38, May 1995.
9. B. Nunes, M. Mendonca, X.-N. Nguyen, K. Obraczka, and K. T. Turletti, " A survey of software-defined networking: Past, present, future of programmable networks," IEEE Commun. Surveys & Tutorials, vol. 16, no. 3, pp. 1617-1634, Third Quarter 2014.
10. C. Papagianni,A. Leivadeas S. Papavassiliou,V. Maglaris,C. Cervello-Pastor,A. Monje On the optimal allocation of virtual resources in cloud computing networks," IEEE Trans. Comput., vol. 62, no. 6, pp. 1060-1071, Jun. 2013.
11. K.-K. Nguyen, M. Cheriet, and Y. Lemieux, "Virtual slice assignment in large-scale cloud interconnects, " IEEE Internet Comput., vol. 18, no. 4, pp. 37-46, Jul./Aug. 2014.
12. C. Li et al., "Software defined environments: An introduction, " IBM J. Res. Develop., vol. 58, no. 2 /3, pp. 1-11, Mar.-May 2014.
13. K. Kerpez and G. Ginis, "Software-defined access network (SDAN), " in Proc. 48th Annu. Conf. Inform. Sci. Sys. (CISS), Mar. 19 -21, 2014, pp. 1-6.
14. E. Lourandakis, R. Weigel, H. Mextorf, and R. Knoechel, " Circuit agility," IEEE Microw. Mag., vol. 13, no. 1, pp. 111-121, Jan./Feb. 2012.
15. D. Laws, W. Miller, M. Richman, and B. Sievers, Advanced Micro Devices (AMD) 22V10 Programmable Ar ray Logic (PAL) Development Team: Oral History Panel. Mountain View, CA, USA: Computer History Museum, Jul. 19, 2012. [Online]. Available: http://www.computerhistory.org.
16. C. M. Christensen, The Innovator's Dilemma: When New Technologies Cause Great Firms to Fail. Boston, MA, USA: Harvard Business School Press, 1997.
17. Fusion Family of Mixed-Signal FPGAs. Aliso Viejo, CA, USA: Microsemi, Mar. 2014, datasheet, (revision 6).
18. M. Mar, B. Sullam, and E. Blom, "An architecture for a configurable mixed-signal device, " IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 565-568, Mar. 2003.
19. T. Toffoli and N. Margolus, "Programmable matter: Concepts and realization, " Physica D, vol. 47, pp. 263-272, 1991.
20. N. Shachtman, "Universal 'Rubik's cube' could become Penta gon shapeshifter," Wired Mag, Jun. 5, 2009. [Online]. Available: http://www.wired.com/2009/06/universalrubiks-cube-could-become-pentagonshapeshifter.
21. H. McCracken, "Project Ara: Inside Google's bold gambi t to make smartphones modular," Time, Feb. 26, 2014. [Online]. Available: http://time.com/10115/google-project-Aramodular-smartphone.
22. Y. L. Tu, S. Q. Xie, and R. Y. K. Fung, "Product development cost estimation in mass customization, " IEEE Trans. Eng. Manag., vol. 54, no. 1, pp. 29-40, Feb. 2007.
23. M. Agrawal and C. Kaushal, "Software effort, quality, cycle time: A study of C MM level 5 projects," IEEE Trans. Softw. Eng., vol. 33, no. 3, pp. 145-156, Mar. 2007.
24. A. Jacobs, C. G. Cieslewski, A. D. George, A. Gordon-Ross, and H. Lam, " Reconfigurable fault tolerance: A comprehensive framework for reliable and adaptive FPGA-based space computing," ACM Trans. Reconfigurable Technol. Syst. (TRETS), vol. 5, no. 4, p. 21, 2012.
25. J. A. Cheatham, J. M. Emmert, and S. Baumgart, " A survey of fault tolerant methodologies for FPGAs," ACM Trans. Design Autom. Electron. Syst. (TODAES), vol. 11, no. 2, pp. 501-533, Apr. 2006.
26. W. B. Cul bertson, R. Amerson, R. J. Carter, P. Kuekes, and G. Snider, " Defect tolerance on the Teramac custom computer," in Proc. 5th Annu. IEEE Symp. Field-Programmable Custom Computing Machines, Apr. 16-18, 1997, pp. 116-123.
27. C. Carmichael, Triple Module Redundancy Design Techniques for Virtex FPGAs. San Jose, CA, USA: Xilinx, 2001, Appl. Note, XAPP197(v1.0).
28. S. Thompson and A. Mycroft, "Self-healing reconfigurable manifolds, " in Proc. Designing Correct Circuits (DCC'06), Mar. 2006.
29. S. Murata, E. Yoshida, A. Kamimura, H. Kurokawa, K. Tomita, and S. Kokaji, " M-TRAN: Self-reconfigurable modular robotic system," IEEE/ASME Trans. Mechatronics, vol. 7, no. 4, pp. 431-441, Dec. 2002.
30. C. Carmichael, Correcting Single Event Upsets Through Virtex Partial Reconfiguration. San Jose, CA, USA: Xilinx, Jun. 1, 2000, Appl. Note XAPP216 (v1.0).
31. M. Wirthlin, " High-reliability FPGA-based systems: Space, high-energy physics, beyond," Proc. IEEE, vol. 103, no. 3, Mar. 2015.
32. S. M. Scalera,J. R. Vazquez The design and implementation of a context switching FPGA in Proc. IEEE Symp. FPGAs for Custom Computing Machines, Apr. 15-17 1998, pp. 78-85.
33. M. J. Wirthlin and B. L. Hutchings, "A dynamic instruction set computer, " in Proc. IEEE Symp. FPGAs for Custom Computing Machines, Apr. 19-21, 1995, pp. 99-107.
34. F. Fons and M. Fons, "Making biometrics the killer app for FPGA dynamic partial reconfiguration, " Xcell J., no. 72, 2010, Xilinx.
35. Enabling 100-Gbit OTN Muxponder Solutions on 28 nm FPGAs. San Jose, CA, USA: Altera, Apr. 2010, White Paper, WP-01126-1.0 (v1.0).
36. P. Clarke, "Tabula tips time-share FPGA architecture, " EE Times, Mar. 1, 2010.
37. S. Trimberger, D. Carberry, A. Johnson, and J. Wong, " A time-multiplexed FPGA," in Proc. 5th Annu. IEEE Symp. Field-Programmable Custom Computing Machines, Apr. 16-18, 1997, pp. 22-28.
38. A. DeHon, "Dynamica lly programmable gate arrays: A step toward increased computational density," in Proc. 4th Canadian Workshop Field-Programmable Devices, 1996, pp. 47-54.
39. M. Hariyama, S. Ogata, M. Kameyama, and M. and Y. Morita, " Design of a multi-context FPGA using a floating-gate-MOS functional pass-gate," in Proc. Asian Solid-State Circuits Conf., Nov. 1-3, 2005, pp. 421-424.
40. L. Zhang and J. S. Dai, "An over view of the development on reconfiguration of metamorphic mechanisms," in Proc. ASME/IFToMM Int. Conf. Reconfigurable Mechanisms and Robots (ReMAR), Jun. 22-24, 2009, pp. 8-12.
41. R. Berger, R. S. Frankel, J. I. Raffel, C. E. Woodward, and P. W. Wyatt, " A laser-programmable multichip module on silicon," in Proc. 5th Annu. IEEE Int. Conf. Wafer Scale Integration, 1993, pp. 30-35.
42. S. M. H. Ho et al., "Structured ASIC: Methodology and comparison, " in Proc. 2010 Int. Conf. Field-Programmable Technol. (FPT), Dec. 8-10, 2010, pp. 377-380.
43. T. C. P. Chau et al., " Design of a single layer programmable structured ASIC library," in Proc. 13th IEEE Int. Symp. Design and Diagnostics of Electronic Circuits and Syst. (DDECS), Apr. 14-16, 2010, pp. 32-35.
44. V. Subramanian et al., " Printed electronics for low-cost electronic systems: Technology status and application development," in Proc. 38th Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 15-19, 2008, pp. 17-24.
45. J. Chang, G. Tong, and E. Sanchez-Sinencio, "Challenges of printed electronics on flexible substrates, " in Proc. 55th IEEE Int. Midwest Symp. Circuits and Syst. (MWSCAS), Aug. 5-8, 2012, pp. 582-585.
46. E. MacDonald et al., " 3D printing for the rapid prototyping of structural electronics," IEEE Access, vol. 2, pp. 234-242, Dec. 2014.
47. L. E. Murr et al., " Microstructures and properties of solid and reticulated mesh components of pure iron fabricated by electron beam melting," J. Mater. Res. Technol., vol. 2, no. 4, pp. 376-385, 2013.
48. C. A. Terrazas et al., " Multi-material metallic structure fabrication using electron beam melting," Int. J. Adv. Manuf. Technol., vol. 71, no. 1-4, pp. 33-45, 2014.
49. P. Hasler and T. S. Lande, "Overview of floating-gate devices, circuits, systems, " IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 1, pp. 1-3, Jan. 2001.
50. G. J. Hu et al., " An advanced CMOS EPROM technology for high speed/high density programmable logic devices and memory applications," in Proc. IEEE Custom Integr. Circuits Conf., May 1-4, 1994, pp. 488-491.
51. J. Rose, A. El Gamal, and A. Sangiovanni-Vincentelli, " Architecture of field-programmable gate arrays," Proc. IEEE, vol. 81, no. 7, pp. 1013-1029, Jul. 1993.
52. G. B. Kenney, W. K. Jones, and R. E. Ogilvie, "Fusing mechanism of nichrome-linked programmable read-only memory devices, " in Proc. 14th Annu. Reliability Physics Symp., Apr. 1976, pp. 164-172.
53. J. Greene,E. Hamdy,S.Beal Antifuse field programmable gate arrays Proc. IEEE, 81, 7, 1042-1056, Jul., 1993.
54. M. A. A. Sanvido, F. R. Chu, A. Kulkarni, and R. Selinger, " NAND flash memory and its role in storage architectures," Proc. IEEE, vol. 96, no. 11, pp. 1864-1874, Nov. 2008.
55. V. Graizer and D. Naccache, "Alien vs. Quine, " IEEE Security & Privacy, vol. 5, no. 2, pp. 26-31, Mar./Apr. 2007.
56. N. Derhacobian, S. C. Hollmer, N. Gilbert, and M. N. Kozicki, " Power and energy perspectives of nonvolatile memory technologies," Proc. IEEE, vol. 98, no. 2, pp. 283-298, Feb. 2010.
57. CoolRunner-II CPLD Family. San Jose, CA, USA: Xilinx, Mar. 2005, Product Documentation (datasheet) DS090 (v2. 3).
58. Y. Pan, G. Dong, and T. Zhang, "Error rate-based wear-leveling for NAND flash memory at highly scaled technology nodes, " IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 7, pp. 1350-1354, Jul. 2013.
59. G. Porter et al., "Integrating microsecond circuit switching into the data center, " ACM SIGCOMM, Hong Kong, China, Aug. 2013.
60. J. I. Dadap et a l., " Modular MEMS-based optical cross-connect with large port-count," IEEE Photon. Technol. Lett., vol. 15, no. 12, pp. 1773-1775, Dec. 2003.
61. IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1, 1990.
62. S. Bayar and A. Yurdakul, " Self-reconfiguration on Spartan-III FPGAs with compressed partial bitstreams via a parallel configuration access port (cPCAP) core," Res. Microelectron. Electron., 2008. PRIME 2008, pp. 137-140, 2008, Ph.D.
63. A. G. Vera, D. Llamocca, M. S. Pattichis, and J. Lyke, " A dynamically reconfigurable computing model for video processing applications," in Proc. 43rd Asilomar Conf. Signals, Syst., Comput., Nov. 1-4, 2009, pp. 327-331.
64. J. Becker, M. Hubner, G. Hettich, R. Constapel, J. Eisenmann, and J. Luka, " Dynamic and partial FPGA exploitation," Proc. IEEE, vol. 95, no. 2, pp. 438-452, Feb. 2007.
65. N. Steiner and P. Athanas, "Hardware autonomy and space systems, " in Proc. 2009 IEEE Aerospace Conf., Mar. 7 -14, pp. 1-13.
66. Equalization for High-Speed Serial Interfaces in Xilinx 7 Series FPGA Transceivers. San Jose, CA, USA: Xilinx, Mar. 27, 2012, White Paper, WP419 (v.1.0).
67. A. Thompson, " Hardware evolution: automatic design of electronic circuits in reconfigurable hardware by artificial evolution," Ph.D. Dissertation, University of Sussex, Sussex, U.K., 1996.
68. R. Lysecky, F. Vahid, and F. S. X.-D. Tan, "Dynamic FPGA routing for just-in-time FPGA compilation, " in Proc. 41st Design Autom. Conf., Jul. 7-11, 2004, pp. 954-959.
69. R. Rubin and A. DeHon, "Choose-your-own-Adventure routing: Lightweight load-time defect avoidance, " in Proc. ACM FPGA'09 Conf., Monterey, CA, USA, Feb. 22-24, 2009.
70. N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed. Addison-Wesley, 2010.
71. A. DeHon, "Unifying mesh-And tree-based programmable interconnect, " IEEE Trans. Very Large Scale Inte gr. (VLSI) Systems, vol. 12, no. 10, pp. 1051-1065, Oct. 2004.
72. S. Cardelli,M. Chiodo, P. Giusto, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli, " Rapid-prototyping of embedded systems via reprogrammable devices," in Proc. 7th IEEE Int. Workshop Rapid System Prototyping, Jun. 19-21, 1996, pp. 133-138.
73. UltraScale Architecture and Product Overview. San Jose, CA, USA: Xilinx, Sep. 16, 2014, Product Documentation, DS890 (v1.4).
74. Zynq-7000 Al Programmable SoC Overview San Jose, CA, USA: Xilinx, Dec. 2013, Product Specification, DS190 (v1.6).
75. Series FPGAs Overview. San Jose, CA, USA: Xilinx, Feb. 2014, Product Specification DS180 (v1.15).
76. Virtex 6 Family Overview. San Jose, CA, USA: Xilinx, Jan. 2012, Product Specification, DS150 (v2.4).
77. Virtex 2.5V Field Programmable Gate Arrays. San Jose, CA, USA: Xilinx, Mar. 2013, Product Specification, DS003-1 (v4.0).
78. Spartan-3 FPGA Family Data Sheet.San Jose, CA, USA: Xilinx, Jun. 2013, Product Specification, DS099.
79. Virtex-4 Family Overview. San Jose, CA, USA: Xilinx, Aug. 2010, Product Specification, DS112 (v3.1).
80. 80] Virtex-5 Family Overview. San Jose, CA, USA: Xilinx, Feb. 2009, Product Specification, DS100 (v5.0).
81. Virtex-6 FPGA Memory Interface Solutions. San Jose, CA, USA: Xilinx, Mar. 2011, Product Specification, DS186 (v1.7).
82. Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions (v2.0). San Jose, CA, USA: Xilinx, Dec. 2013, Advance Product Specification, DS176 (v2.0).
83. I. Kuon and J. Rose, "Area and delay trade-offs in the circuit and architecture design of FPGAs, " in ACM Symp. FPGAs, Feb. 2008, pp. 149-158.
84. Spartan-6 FPGA DSP48A1 Slice. San Jose, CA, USA: Xilinx, May 29, 2014, Product Documentation UG389 (v1.2).
85. Quartus II Development Software Handbook v11.0. San Jose, CA, USA: Altera, Nov. 2011, Product Documentation.
86. Xilinx Integrated Software Environment (ISE) Design Suite Documentation. San Jose, CA, USA: Xilinx, May 3, 2010, Product Documentation. [Online]. Available : http://www.xilinx.com.
87. J. S. Small, "General-purpose electronic analog computing: 1945-1965, " IEEE Ann. History of Computing, vol. 15, no. 2, pp. 8-18, 1993.
88. S. H aykin, Neural Networks: A Comprehensive Foundation, 3rd ed. Upper Saddle River, NJ, USA: Prentice-Hall, 2007.
89. C. Mead, "Neuromorphic electronic systems, " Proc. IEEE, vol. 78, no. 1 0, pp. 1629-1636, Oct. 1990.
90. A. Malcher and P. Falkowski, "Analog reconfigurable circuits, " Int. J. Electron. Telecommun., vol. 60, no. 1, pp. 8-19, 2014.
91. L. H. Crockett, R. A. Elliot,M. A. Enderwitz, and R. W. Stewart, The Zynq Book. Glasgow, U.K.: Strathclyde Academic Media, 2014. [Online]. Available: http://www.zynqbook.com.
92. SmartFusion2 Product Brief. Mountain View, CA, USA: Microsemi Corp., Aug. 2014, Product Documentation.
93. G. Kapur and C. M. Markan, "Design methodology for analog circuit designs using proposed field programmable basic analog building blocks," in Proc. 2011 Int. Conf. Field-Programmable Technol. (FPT), Dec. 12-14, pp. 1-4.
94. E. K. F. Lee, " Reconfigurable analog integrated circuit architecture based on switched-capacitor techniques," in Proc. 8th IEEE Int. Conf. Innovative Systems in Silicon, Oct. 9-11, 1996, pp. 148-158.
95. M. A. Trefzer, J. A. Walker, and A.M. Tyrrell, "A programmable analogue and digital array for bio-inspire d electronic design optimization at nano-scale silicon technology nodes," in Proc. 45th Asilomar Conf. Signals, Syst., Comput., Nov. 6-9, 2011, pp. 1537-1541.
96. R. Williams How we found the missing memristor IEEE Spectrum 45, 12,28-35 Dec., 2008
97. J. Hutchby and M. Garner, "Assessment of the potential & maturity of selected emerging r esearch memory technologies," in Proc. Int. Technology Roadmap for Semiconductors (ITRS) Workshop and ERD/ERM Working Group Meeting, 2010. [Online]. Available: http://www.itrs.net/Links/2010ITRS/2010Update/ToPost/ERD-ERM-2010FINALReportMemo ryAssessment-ITRS.pdf.
98. E. K. F. Lee and P. G. Gulak, "A CMOS field-programmable analog array, " IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1860-1867, Dec. 1991.
99. I. Parberry, Circuit Complexity and Neural Networks. Cambridge, MA, USA: MIT Press, Jul. 1994.
100. A. Stoica, R. Zebulum, D. Keymeulen, R. Tawel, T. Daud, and A. Thakoor, " Reconfigurable VLSI architectures for evolvable hardware: From experimental field programmable transistor arrays to evolution-oriented chips," IEEE Trans. Very Large Scale Integr. (VLSI) Systems, vol. 9, no. 1, pp. 227-232, Feb. 2001.
101. S. Yang, "Logic Synthesis and Optimization Benchmarks, Version 3.0, " Microelectronics Center of North Carolina, Tech. Rep. [Online]. Available: http://jupite r3.csc. ncsu.edu/~brglez/Cite-BibFiles-Reprintshome/Cite-BibFiles-Reprints-Central/BibValidateCentralDB/Cite-ForWebPosting/1991-IWLSUG-Saeyang/1991-IWLSUGSaeyang-guide.pdf
102. G. M. Rebeiz et al., "Tuning in to RF MEMS, " IEEE Micro, vol. 10, no. 6, pp. 55-72, Oct. 2009.
103. M. Rais-Zadeh, J. Fox, D. Wentzloff, and Y. Gianchandani, " Reconfigurable radios: A possible solution to reduce entry costs in wireless phones," Proc. IEEE, vol. 103, no. 3, Mar. 2015.
104. J. Costantine, Y. Tawk, S. Barbin, and C. G. Christodoulou, " Reconfigurable antennas: Design and applications," Proc. IEEE, vol. 103, no. 3, Mar. 2015.
105. I. Koren, F. Demmerle, R. May, M. Kaibel, and S. Sattler, " FPGA Architecture for RF transceiver system and mixed-signal low cost tests," in Proc. 12th IEEE European Test Symp. (ETS '07), May 20-24, 2007, pp. 43-48.
106. M. Lee, R. Lucas, R. Young, R. Howell, P. Borodulin, and N. El-Hinnawy, " RF FPGA for 0.4 to 18 GHz DoD multi-function systems," in Proc. 38th Government Microcircuit Appl. and Critical Technology Conf. Microelectronics for Net-Enabled and Cyber Transformational Technologies (GOMACTech-13), Mar. 11 -14, 2013, pp. 111-113.
107. 07] G. M. Rebeiz and J. B. Muldavin, "RF MEMS switches and switch circuits, " IEEE Microw. Mag, vol. 2, no. 4, pp. 59-71, Dec. 2001.
108. E. R. Brown, "RF-MEMS switches for reconf igurable integrated circuits," IEEE Trans. Microw. Theory Tech., vol. 46, no. 11, pp. 1868-1880, Nov. 1998.
109. C. G. Christodoulou, Y. Tawk, S. A. Lane, and S. R. Erwin, " Reconfigurable antennas for wireless and space applications," Proc. IEEE, vol. 100, no. 7, pp. 2250-2261, Jul. 2012.
110. Y.-S. Lee and A. C. H. Wu, "A performance and routability-driven router for FPGAs considering path delays, " IEEE Trans. Comput.-Aided Design of Integr. Circuits and Syst., vol. 16, no. 2, pp. 179-185, Feb. 1997.
111. J. Cost antine, Y. Tawk, and C. Christodoulou, Design of Reconfigurable Antennas Using Graph Models. San Rafael, CA, USA: Morgan & Claypool, Jul. 2013.
112. A. Ocera, P. Farinelli, P. Mezzanotte, R. Sorrentino, B. Margesin, and F. Giacomozzi, " Novel RF-MEMS widely-reconfigurable directional coupler," in Proc. 2007 Eur. Microwave Conf., Oct. 9-12, pp. 122-125.
113. A. Ocera, P. Farinelli, F. Cherub ini, P. Mezzanotte, R. Sorrentino, B. Margesin, and F. Giacomozzi, " A MEMS-reconfigurable power divider on high resistivity silicon substrate," in Proc. 2007 Int. Microwave Symp. (IEEE/MTT-S), Jun. 3-8, 2007, pp. 501-504.
114. L. Xing, M. Kintis, C. Hansen, W. Chan, G. Tseng, and M. Tan, " A simple DC to 110 GHz MMIC true time delay line," IEEE Microw. Wireless Compon. Lett., vol. 22, no. 7, pp. 369-371, Jul. 2012.
115. V. Yousefzadeh, N. Wang, D. Maksimovic, and Z. Popovic, " Digitally controlled DC-DC converter for RF power amplifier," in Proc. 19th Annu. IEEE Applied Power Electronics Conf. and Ex 2004 (APEC '04), pp. 81-87.
116. V. Murray, D. Llamocca, J. Lyke, K. Avery, Y. Jiang, and M. Pattichis, " Cell-based architecture for adaptive wiring panels: A first prototype," J. Aerosp. Inf. Syst., vol. 10, no. 4, Apr. 2013.
117. C. R. Giles,B. Barber,V. Aksyuk,R. Ruel,L. Stulz,D. Bishop Reconfigurable 16-channel WDM drop module using silicon MEMSoptical switches IEEE Photon. Technol. Lett. 11, 1, 63-65, Jan., 1999.
118. D.-Y. Zhang, N. Justis, and Y.-H. Lo, "Integrated fluidic lenses and optic systems, " IEEE J. Sel. Topics Quantum Electron., vol. 11, no. 1, pp. 97-106, Jan./Feb. 2005.
119. R. Marks, D. L. Mathine, G. Peyman, J. Schwiegerling, and N. Peyghambarian, " Adjustable fluidic lenses for ophthalmic corrections," Opt. Lett., vol. 34, no. 4, pp. 515-517, 2009.
120. Z. Chenglong, L. Yongmin, Z. Yanhui, N. Fang, and T. J. Huang, " A reconfigurable plasmofluidic lens," Nature Commun., Aug. 4, 2013.
121. R. Soref, private communication, Sep. 2010.
122. R. Soref, "Reconfigurable integrated optoelectronics, " Adv. OptoElectron., vol. 2011, no. 627802, pp. 1-15, 2011.
123. Z. Li, S. Le Beux, C. Monat, X. Letartre, and I. O'Connor, " Optical look up table," in Proc. Design Automation Test Eur. (DATE), Mar. 18-22, 2013, pp. 873-876.
124. Z. Dengke, X. Feng, and H. Yidong, "Tunable and reconfigurable bandpass microwave photonic filters utilizing integrated optical processor on silicon-on-insulator substrate," IEEE Photon. Technol. Lett., vol. 24, no. 17, pp. 1502-1505, Sep. 2012.
125. L. Berthelon et al., "Towards photonic networking: Exp erimental demonstration of a reconfigurable survivable WDM ring network," in Proc. Global Telecommun. Conf., 1996 (GLOBECOM '96), Nov. 18-22, pp. 311-315.
126. G. Wang et al., "Your data center is a router: The case for reconfigurable optical circuit switched paths," in Proc. ACM Hotnets-VIII, New York, NY, USA, Oct. 2009.
127. J. W. Clement and D. E. Brei, "Proof-of-concept investigation of active velcro for sma rt attachment mechanisms," in AIAA 42nd Structures, Structural Dynamics, Materials Conf. and Exhibit, Apr. 16-19, 2001.
128. W. Kaal and S. Herold, "Electroactive polymer actuators in dynamic applications, " IEEE/ASME Trans. Mechatron., vol. 16, no. 1, pp. 24-32, Feb. 2011.
129. S. Murata and H. Kurokawa, "Self-reconfigurable robots, " IEEE Robotics Autom. Mag., vol. 14, no. 1, pp. 71-78, Mar. 2007.
130. W. Hongxing, C. Yingpeng, L. Haiyuan, L. Dezhong, and W. Tianmiao, " Sambot: A self-Assembly modular robot for swarm robot [sic]," in Proc. 2010 IEEE Int. Conf. Robotics and Automation (ICRA), May 3-7, pp. 66-71.
131. H. Huang, L. Bing, L. Rongqiang, and D. Zongquan, "Type synthesis of deployable/foldable articulated mechanisms, " in Proc. 200 Int. Conf. Mechatr onics Autom. (ICMA), Aug. 4-7, pp. 991-996.
132. D. Little and J. Walter, "Using hexagonal metamorphic robots to form temporary bridges, " in Proc. 2005 IEEE/RSJ Int. Conf. Intelligent Robots and System s, Aug. 2-6, pp. 2893-2898.
133. J. Lyke, "Cellular-satellite, a different kind of final frontier, " in AIAA 22nd Annu. Conf. Small Satellites, Aug. 11-14, 2008.
134. Y. Guan, L. Jiang, X. Zhang, X. Zhang, and X. Zhou, " Development of novel robots with modular methodology," in Proc. IEEE/RSJ Int. Conf. Intelligent Robots and Systems 2009 (IROS 2009), Oct. 10-15, pp. 2385-2390.
135. M. Yim, Z. Ying, K. Roufas, D. Duff, and C. Eldershaw, " Connecting and disconnecting for chain self-reconfiguration with PolyBot," IEEE/ASME Trans.Mechatron., vol. 7, no. 4, pp. 442-451, Dec. 2002.
136. W. Zhang Wuxiang and D. Xilun, "A method for designing metamorphic mechanisms and its application, " in Proc. ASME/IFToMM Int. Conf. Reconfigurable Mechanisms and Ro bots 2009 (ReMAR 2009), Jun. 2009, pp. 171-174.
137. G. Brault, "Guided self-Assembly for protosat combination, " AIAA 2003 Responsive Space Conf., Apr. 1-3, 2003, paper RS1-2003-4002. [Online]. Available: http://www.responsivespace.com/Papers/RS1/SESSION4/BLASE/4002P.pdf.
138. C. McGray,D. Rus Self-reconfigura ble molecule robots as 3D metamorphic robots in Proc. 1998 IEEE/RSJ Int. Conf. Intell. Robots Syst., Oct. 13-17 837-842.
139. H. Mabed and J. Bourgeois, "Towards programmable material : Flexible distributed algorithm for modular robots shape shifting," in 2014 IEEE/ASME Int. Conf. Adv. Intell. Mechatronics (AIM), Besancon, France, Jul. 8-11, 2014, pp. 408-414.
140. W. Qiuxuan, L. Sh irong, C. Guanyi, and Y. Fei, " Mechatronics design of a modular self-reconfigurable and self-repair robot," in Proc. 2007 IEEE Int. Conf. Control and Automation (ICCA 2007), May 30-Jun. 1, pp. 2243-2247.
141. P. Pillai, J. Campbell, G. Kedia, S. Moudgal, and K. Sheth, " A 3D fax machine based on claytronics," in Proc. 2006 IEEE/RSJ Int. Conf. Intelligent Robots and Systems, Oct. 9-15, pp. 4728-4735.
142. J. Bourgeois and S. C. Goldstein, "Distributed intelligent MEMS: Progresses and perspectives, " IEEE Syst. J., 2013, 150, pp. 15-25.
143. C. K. Fredrickson and Z. H. Fan, "Macro-to-micro interfaces for microfluidic devices, " Laboratory on a Chip, vol. 4, no. 6, pp. 526-533, 2004.
144. E. Verpoorte and N. F. Rooij, "Microfluidics meets MEMS, " Proc. IEEE, vol. 91, no. 6, pp. 930-953, Jun. 2003.
145. J. P. Wikswo et al., " Scaling and systems biology for integrating multiple organs-on-A-chip," Laboratory on a Chip, vol. 13, no. 18, pp. 3496-3511, 2013.
146. J. Lyke, W. G. Wilson, and J. W. Tringe, "Aerospace applications, " in MEMS Packaging, T.-R. Hsu, Ed. London, U.K.: The Institution of Electrical Engineers (INSPEC), 2004.
147. D. Bugby, W. Zimbeck, and E. Kroliczek, "Modular two-phase heat transfer based architecture for future responsive spacecraft, " in Proc. 49th AIAA/ASME/ASCE/AHS/ASC Structures, Structural Dynamics, Materials Conf., Apr. 7-10, 2008.
148. H. Darabi, A. Mirzaei, and M. Mikhemar, " Highly integrated and tunable RF front ends for reconfigurable multiband transceivers: A tutorial," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 9, pp. 2038-2050, Sep. 2011.
149. F. Semperlotti and H. Zhu, " Achieving selective interrogation and sub-wavelength resolution in thin plates with embedded metamaterial acoustic lenses, " J. Appl. Phys., vol. 116, no. 054906, 2014.
150. D. R. Smith, W. J. Padilla, D. C. Vier, S. C. Nemat-Nasser, and S. Schultz, " Composite medium with simultaneously negative permeability and permittivity," Phys. Rev. Lett., vol. 84, no. 18, pp. 4184-4187, May 2000.
151. R. A. Shelby, D. R. Smith, and S. Schultz, "Experimental verification of a negative index of refraction, " Science, vol. 292, no. 5514, pp. 77-79, Feb. 2001.
152. J. B. Pendry, "Extremely low frequency plasmons in metallic mesostructures, " Phys. Rev. Lett., vol. 76, no. 25, pp. 4773-4776, Jun. 1996.
153. J. B. Pendry, A. J. Holden, D. J. Robbins, and W. J. Stewart, " Magnetism from conductors and enhanced nonlinear phenomena," IEEE Trans. Microwave Theory Tech., vol. 47, no. 11, pp. 2075-2084, Nov. 1999.
154. Q. Wu, M. Wu, F. Meng, J. J. Wu, and L. Li, " Modeling the effects of an individual SRR by equivalent circuit method," in IEEE AP-S Int. Symp. Dig., Jul. 2005, pp. 631-634.
155. A. A. Grbic and G. V. Eleftheriades, " Experimental verification of backward-wave radiation from a negative refractive index metamaterial," J. Appl. Phys, vol. 92, pp. 5930-5935, 2002.
156. K. Aydin, I. Bulu, K. Guven, M. Kafesaki, C. M. Soukoulis, and E. Ozbay, " Investigation of magnetic resonances for different split-ring resonator parameters and designs, " New J. Phys, vol. 7, no. 168, pp. 1-15, Aug. 2005.
157. R. W. Zio lkowski and F. Auzanneau, "Passive artificial molecule realizations of dielectric materials, " J. Appl. Phys., vol. 82, no. 7, pp. 3195-3198, 1997.
158. Z. L. Samson et al., "Metamaterial e lectro-optic switch of nanoscale thickness," Appl. Phys. Lett., vol. 96, no. 143105, 2010.
159. A. B. Golovin and O. D. Lavrentovich, "Electrically reconfigurable optical metamaterial based on colloida l dispersion of metal nanorods in dielectric fluid," Appl. Phys. Lett., vol. 95, no. 25, Dec. 2009, Art. ID. 254104-1-254104-3.
160. J. Perruisseau-Carrier,T. Lisec,A. K. Skrivervk Circuit model and design of silicon-integrated CRLH-TLS analogically controlled by MEMS Microw. Opt. Technol. Lett. 48 12 2496-2499 2006.
161. J. Pappalardo, "Polar printer reimag ines the way magnets work," Popular Mechanics, Dec. 18, 2009.
162. D. Rodrigo and L. Jofre, "Frequency and radiation pattern reconfigurability of a multi-size pixel antenna, " IEEE Trans. Antennas Pro pag., vol. 60, no. 5, pp. 2219-2225, May 2012.
163. J. Cong, L. Bin, S. Neuendorffer, J. Noguera, K. Vissers, and Z. Zhiru, " High-level synthesis for FPGAs: From prototyping to deployment," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 30, no. 4, pp. 473-491, Apr. 2011.
164. J. Cong and K. Minkovich, "Optimality study of logic synthesis for LUT-based FPGAs, " IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 2, pp. 230-239, Feb. 2007.
165. J. L. Hennessey and D. A. Patterson, Computer Architecture, 5th ed. Burlington, MA, USA: Morgan Kaufmann, Sep. 2011.
166. S. R. Subramanya and B. K. Yi, "Mobile communicationsVAn overview, " IEEE Potentials, vol. 24, no. 5, pp. 36-40, Dec. 2005.
167. T. C.Waugh, " Field programmable gate array key to reconfigurable array outperforming supercomputers," in Proc. IEEE 1991 Custom Integr. Circuits Conf., 1991, May 12-15, 1991, pp. 6.6:1 -6.6:4.
168. A. DeHon, "Fundamental underpinnings of reconfigurable computing architectures, " Proc. IEEE, vol. 103, no. 3, Mar. 2015.
169. R. Tessier, K. Pocek, and A. DeHon, "Reconfigurable computing architectures, " Proc. IEEE, vol. 103, no. 3, Mar. 2015.
170. N.-Y. Xu, X.-F. C ai, R. Gao, L. Zhang, and F.-H. Hsu, " FPGA acceleration of rankboost in web search engines," ACM Trans. Reconfig. Technol. Syst., vol. 1, no. 4, Jan. 2009, article 19.
171. R. Merrit and Rick, " M'soft plugs FPGAs in datacenter," EE Times, Aug. 12, 2014. [Online]. Available: http://www.eetimes. com/document.asp?doc-id=1323500.
172. A. Regalado, "Who coined 'cloud computing, " MIT Technol. Rev., Oct. 31, 2011.
173. D. Drutskoy, E. Keller, and J. Rexford, "Scalable network virtualization in software-defined networks, " IEEE Internet Comput., vol. 17, no. 2, pp. 20-27, Mar./Apr. 2013.
174. C. Papagianni, A. Leivadeas, S. Papavassiliou, V. Maglaris, C. Cervello-Pastor, and A. Monje, " On the optimal allocation of virtual resources in cloud computing networks," IEEE Trans. Comput., vol. 62, no. 6, pp. 1060-1071, Jun. 2013.
175. M. N. O. Sadiku, S. M. Musa, and O. D. Momoh, "Cloud computing: Opportunities and challenges, " IEEE Po tentials Mag, vol. 33, no. 1, pp. 34-36, Jan./Feb. 2014.
176. D. Kreutz, F. M. V. Ramos, P. E. P. Verissimo, C. E. Rothenberg, S. Azodolmolky, and S. Uhlig, " Software-defined networking: A comprehensive survey," Proc. IEEE, vol. 103, no. 1, Jan. 2015.
177. J. Mitola, A. Attar, H. Zhang, O. Holland, H. Harada, and H. Aghvami, " Achievements and the road ahead: The first decade of cognitive radio," IEEE Trans. Veh. Technol., vol. 59, no. 4, pp. 1574-1577, May 2010.
178. P. F. Marshall, "Extending the reach of cognitive radio, " Proc. IEEE, vol. 97, no. 4, pp. 612-625, Apr. 2009.
179. R. G. Machado and A. M. Wyglinski, "Software-defined radio: Bridging the analog-digital divide, " Proc. IEEE, vol. 103, no. 3, Mar. 2015.
180. S. Shelley, J. Costantine, C. G. Christodoulou, D. E. Anagnostou, and J. C. Lyke, " Controlling switch-reconfigured antennas using FPGAs," in Proc. 2010 IEEE Antennas Propag. Soc. Int. Symp. (APSURSI), pp. 1-4.
181. R. Max,Y. Sun,T. Goodwin,H. Turner,J. Reed,J. White Software frameworks for SDR Proc. IEEE 103 3, Mar. 2015.
182. B. Fuller, "Do we need a 'glue' engineer? " Semicond. Eng., Mar. 13, 2014.
183. C. Dongye, "Design of the on-chip bus based on Wishbone, " in Proc. 2011 Int. Conf. Electronics, Commun. Control (ICECC), Sep. 9-11, pp. 3653-3656.
184. Looper, Modem Song. London, U.K.: Jeepster Recordings, 2000, CD format.
185. V. Vinge, Rainbow's End. New York, NY, U SA: Tor Books, 2006.
186. J. E. Hopcroft and R. L. Mattson, "Synthesis of minimal threshold logic networks, " IEEE Trans. Electron. Comput., vol. EC-14, no. 4, pp. 552-560, Aug. 1965.
187. M. A. Bawiec and M. Nikodem, "Boolean logic function synthesis for generalised threshold gate circuits, " in Proc. 46th ACM/IEEE Design Automation Conf. 2009 (DAC '09), Jul. 26-31, pp. 83-86.
188. R. A. Rutenbar, G. G. E. Gielen, and J. Roychowdhury, " Hierarchical modeling, optimization, synthesis for system-level analog and RF designs," Proc. IEEE, vol. 95, no. 3, pp. 640-669, Mar. 2007.
189. P. Nuzzo, A. Sangiovanni-Vincentelli, X. Sun, and A. Puggelli, " Methodology for the design of analog integrated interfaces using contracts," IEEE Sensors J., vol. 12, no. 12, pp. 3329-3345, Dec. 2012.
190. S. A. Huss, "Analog circuit synthesis: A search for the holy grail? " in Proc. 2006 IEEE Int. Symp. Circuits and Syst. ( ISCAS 2006), May 21-24, pp. 1466.
191. M. Mar, B. Sullam, and E. Blom, "An architecture for a programmable mixed-signal device, " in Proc. IEEE 2002 Custom Integrated Circuits Conf, 2002, pp. 55-58.
192. AN231E04 Datasheet rev 1.2 3rd Generation Dynamically Reconfigurable dpASP. Mesa, AZ, USA: Anadigm, 2014, Product Documentation.
193. Anadigm Apex dpASP Family User Manual. Mesa, AZ, USA: Anadigm, 2014, Product Documentation.
194. G. D. Asensi, J. S. Gomez-Diaz, J. Martinez-Alajarin, and R. R. Merino, " Synthesis on programmable analog devices from VHDL-AMS," in Proc. IEEE Mediterranean Electrotechnical Conf. (MELECON 2006), May 16-19, 2006, pp. 27-30.
195. A. Sangiovanni-Vincentelli, A. El Gamal, and J. Rose, " Synthesis method for field programmable gate arrays," Proc. IEEE, vol. 81, no. 7, pp. 1057-1083, Jul. 1993.
196. J. P. Roth and R. M. Karp, "Minimization over boolean graphs, " IBM J. Res. Develop., vol. 6, no. 2, pp. 227-238, Apr. 1962.
197. R. E. Bryant, "Graph-based algorithms for boolean function manipulation, " IEEE Trans. Comput., vol. c-35, no.8, pp. 677-691, Aug. 1986.
198. IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis, IEEE Standard 1076.6-2004, 2004.
199. IEEE Standard for Veril og Hardware Description Language, IEEE Standard 1364-2005, 2006.
200. T. Cooklev, R. Normoyle, and D. Clendenen, "The VITA 49 analog RF-digital interface, " IEEE Circuits Syst. Mag, vol. 12 , no. 4, pp. 21-32, Fourth Quarter, 2012.
201. R. Morris, E. Kohler, J. Jannotti, and M. F. Kaashoek, "The Click modular router, " ACM Trans. Computer Syst. (TOCS), vol. 18, pp. 263-297.
202. N. Shah,W. Plishker,K. Ravindran,K. Keutzer NP-Click: A productive software development approach for network processors IEEE Micro 24 5 45-54, Sep.-Oct. 2004.
203. W.-J. Fang and A. C.-H. Wu, "Integrating HDL synthesis and partitioning for multi-FPGA designs, " IEEE Des. Test Comput., vol. 15, no. 2, pp. 65-72, Apr.-Jun. 1998.
204. S. P. Swaminathan, P.-C. K. Lin, and S. P. Khatri, "Timing aware partitioning for multi-FPGA based logic simul ation using top-down selective hierarchy flattening," in Proc. 2012 IEEE 30th Int. Conf. Comput. Design (ICCD), pp. 153-158.
205. A. Narula-Tam, P. J. Lin, and E. Modiano, "Efficient routing and wavelength assignment for reconfigurable WDM networks, " IEEE J. Sel. Areas Commun., vol. 20, no. 1, pp. 75-88, Jan. 2002.
206. A. Sangiovanni-Vincentelli, "Quo Vadis, SL D? Reasoning about the trends and challenges of system level design," Proc. IEEE, vol. 95, no. 3, pp. 467-506,Mar. 2007.
207. R. Chaware, K. Nagarajan, and S. Ramalingam, "Assembly and rel iability challenges in 3D integration of 28 nm FPGA die on a large high density 65 nm passive interposer," in Proc. 2012 IEEE 62nd Electron. Components Technol. Conf. (ECTC), pp. 279-283.
208. S. M. Satheesh and E. Salman, "Power distribution in TSV-based 3-D processor-memory stacks, " IEEE J. Emerging Sel. Topics Circuits Syst., vol. 2, no. 4, pp. 692-703, Dec. 2012.
209. S. L. Pei-Siang, F. X. Che, C. S. Choong, M. C. B. Rong, V. N. Sekhar, V. S. Rao, and C. T. Chong, " Heterogeneous three-layer TSV chip stacking assembly with moldable underfill," IEEE Trans. Compon., Packag. Manuf. Technol., vol. COMML-3, no. 11, pp. 1960-1970, Nov. 2013.
210. R. S. Patti, " Three-dimensional integrated circuits and the future of system-on-chip designs," Proc. IEEE, vol. 94, no. 6, pp. 1214-1224, Jun. 2006.
211. J. Lyke, "Reconfigurable cellular arrays for molecular electronics, " Ph.D. dissertation, ECE Dept., UNM, Albuquerque, NM, 2004.
212. I. Kuon, R. Tessier, and J. Rose, "FPGA architecture: Survey and challenges, " Foundations and Trends Electron. Des. Autom., vol. 2, no. 2, pp. 135-253, 2008. [Online]. Available: http://www.nowpublishers.com/article/Details/EDA-005.
213. M. Minsky and S. Papert, Perceptrons. An Introduction to Computational Geometry. Cambridge, MA, USA: M.I.T. Press, 1969.
214. V. Vapnik and A. Chervonenkis, "On the uniform convergence of relative frequenci es of events to their probabilities.," Theory of Probability and Its Applications, vol. 16, no. 2, pp. 264-280, 1971.
215. L. Deng, "The MNIST database of handwritten digit images for machine learning research," IEEE Signal Process. Mag, vol. 29, no. 6, pp. 141-142, Nov. 2012.
216. J. Luu, J. H. Anderson, and J. S. Rose, " Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect," in Proc. 19th ACM/SIGDA Int. Symp. Field Programmable Gate Arrays, 2011, pp. 227-236.
217. J. Rose, J. Luu, C.-W. Yu, O. Densmore, J. Goeders, A. Somerville, K. B. Kent, P. Jamieson, and J. Anderson, " The VTR project: Architecture and CAD for FPGAs from Verilog to routing," in Proc. ACM Symp. FPGAs, Feb. 2012, pp. 77-86.
218. V. Betz and J. Rose, "How much logic should go in an FPGA logic block, " IEEE Des. Test Comput., vol. 15, no. 1, pp. 10-15, Jan.-Mar. 1998.
219. A. DeHon, " Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)," in Proc. 1999 ACM/SIGDA 7th Int. Symp. Field programmable gate arrays (FPGA '99), pp. 69-78.
220. Y.-L. Wu, D. Chang, M. Marek-Sadowska, and S. Tsukiyama, " Not necessarily more switches more routability [sic.]," in Proc. 1997 Asia and South Pacific Design Autom. Conf., Jan. 28-31, pp. 579-584.
221. S. M. Trimberger and S. M. J. J. Moore, "FPGA security: Motivations, features, applications, " Proc. IEEE, vol. 102, no. 8, pp. 1248-1265, Aug. 2014.
222. E. Peterson, Developing Tamper Resistant Designs With Xilinx Virtex-6 and 7 Series FPGAs. San Jose, CA, USA: Xilinx, Oct. 2013, Application Note XAPP1084 (v1.3).
223. S. Skorobogatov and C. Woods, "Breakthrough silicon scanning discovers backdoor in military chip, " in Proc. Cryptographic Hardware and Embedded Systems Workshop (CHES-2012), Sep. 9-12, 2012, pp. 23-40978-3-642-33026-1, Leuven, Belgium, LNCS 7428, Springer.
224. Microsemi ProASIC3 FPGA Security Overview Mountain View CA USA Microsemi Corporation Sep. 5 2012, Press Release.