Self-reconfiguration on Spartan-III FPGAs with compressed partial bitstreams via a Parallel Configuration Access Port (cPCAP) core

PRIME - 2008 PhD Research in Microelectronics and Electronics, Proceedings

Volumn , Issue , 2008, Pages 137-140

  Bayar, Salih ^a   Yurdakul, Arda ^a  

^a BOGAZICI UNIVERSITY   (Turkey)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS CONTROL; ELECTRONICS INDUSTRY; MICROELECTRONICS; MODULAR ROBOTS; PORTS AND HARBORS;

ALTERNATIVE APPROACH; BIT STREAMS; EMBEDDED PROCESSORS; FIELD PROGRAMMABLE GATE ARRAY; FPGA ARCHITECTURES; PARALLEL CONFIGURATION; RUN-TIME; SELF-RECONFIGURATION; SPARTAN-3; VIRTEX-4; VIRTEX-II;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 51849108507     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RME.2008.4595744     Document Type: Conference Paper

References (11)

1. Salih Bayar and Arda Yurdakul. Dynamic Partial Self-Reconfiguration on Spartan-III FPGAs via a Parallel Configuration Access Port (PCAP). HIPEAC2008, Gothenburg, Sweden, January 2008.
2. Ivan Gonzalez, Estanislao Aguayo, and Sergio Lopez-Buedo. SeIf-reconfigurable embedded systems on low-cost fpgas. IEEE Micro, pages 49 - 57, July-Aug. 2007.
3. K. Paulsson, M. Hübner, G. Auer, M. Dreschmann, L. Chen, and J. Becker. Implementation of a Virtual Internal Configuration Access Port (JCAP) for enabling Partial Self-Reconfiguration on Xilinx Spartan-III FPGAs. FPL, Amsterdam, Netherland, August 2007.
4. Katarina Paulsson, Michael Hübner, Salih Bayar, and Jürgen Becker. Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. ReCoSoc2007, Montpellier, France, June 2007.
5. Xilinx. Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode. XAPP502, (v1.4) edition, November, 13 2002.
6. Xilinx. Two Flows for Partial Reconfiguration: Module Based or Difference Based. XAPP290, (v1.2) edition, September, 9 2004.
7. Xilinx. Spartan-3 Generation Configuration User Guide. UG332, (v1.2) edition, May, 23 2007.
8. Xilinx. Virtex-4 Configuration Guide. UG071, (v1.9) edition, October, 1 2007.
9. Xilinx. Virtex-5 FPGA Configuration User Guide. UG191, (v2.5) edition, October, 10 2007.
10. Xilinx. Virtex-II Platform FPGA User Guide. UG002, (v2.1) edition, 28 March 2007.
11. Xilinx. Virtex-II Pro and Virtex-II Pro X FPGA User Guide. UG012, (v4.1) edition, 28 March 2007.